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  1. #1
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    Parameter location in a Verilog Module

    Hello,

    Code:
    I noticed that in Verilog both of the constracts below compile correctly.
    // some_parameter is used after some_input
    module some_module 
    #(
        parameter some_parameter 
    )
    (
        input some_input [ some_parameter : 0 ]                       
    ) ;
    endmodule
    
    // some_parameter is used before some_input
    module some_module 
    #(
        parameter some_parameter 
    )
    (
        input [ some_parameter : 0 ] some_input                        
    ) ;
    endmodule
    Are they equivalent ?

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  2. #2
    Advanced Member level 5
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    Re: Parameter location in a Verilog Module

    First one is an unpacked array, 2nd one is a packed array.
    https://www.verilogpro.com/systemver...synthesizable/


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