quyleanh
Member level 3
In order to prevent atenna effect, there are 4 methods which I know.
1. Metal jumper
2. Poly gate area modification
3. Add diode cell protection. (N+/PW for NMOS; P+/NW for PMOS)
4. Add well ring to create junction like diode protection. (Nwell ring for NMOS, Pwell ring for PMOS)
In the method 3, 4, could you tell me what is different between them? Thank you very much.
I see in some cases, designer decides to add a diode cell instead of drawing a well ring.
1. Metal jumper
2. Poly gate area modification
3. Add diode cell protection. (N+/PW for NMOS; P+/NW for PMOS)
4. Add well ring to create junction like diode protection. (Nwell ring for NMOS, Pwell ring for PMOS)
In the method 3, 4, could you tell me what is different between them? Thank you very much.
I see in some cases, designer decides to add a diode cell instead of drawing a well ring.