groover
Junior Member level 1
Hi, I am learning Verilog and struggling with an aspect. I have an 8MHz clock and I have an external signal called Rxd. I need to detect a falling edge on this signal and reset a counter. It could be anywhere from ns to hours before the falling edge appears.
I have:
I then look for the falling edge:
This works but the problem is that it delays detection of the falling edge by up to one clk period. I need the delay from the edge to resetting the counter to be as short as possible. Is there a better way of doing this?
Thanks!
I have:
Code:
reg Rxd_Buf;
always @ (posedge clk) begin
Rxd_Buf <= { Rxd };
...
end
I then look for the falling edge:
Code:
if (RxdBuf == 1'b0 && !RxD) begin
...
end
This works but the problem is that it delays detection of the falling edge by up to one clk period. I need the delay from the edge to resetting the counter to be as short as possible. Is there a better way of doing this?
Thanks!