msdarvishi
Full Member level 4
Dear all,
I am working with Vivado 2017.3 targeting a KC705 FPGA.
I have a design including a Microblaze, an AXI_PCIe, and a MIG 7SEries DDR3 memory. Both Microblaze and DDR3 can read/write data from/to DDR3 and it works very well.
Now, I have added a JESD204 module and implemented my design. I am wondering whether there is a way to fetch data already written in DDR3 from this module and put it at the head of JESD204 (feeding it to the JESD204 module).
Is it possible or a way to do it? I was thinking to AXI_DMA but I am not sure where it is the solution or not.
Any help and guide are in advance appreciated.
Bests,
I am working with Vivado 2017.3 targeting a KC705 FPGA.
I have a design including a Microblaze, an AXI_PCIe, and a MIG 7SEries DDR3 memory. Both Microblaze and DDR3 can read/write data from/to DDR3 and it works very well.
Now, I have added a JESD204 module and implemented my design. I am wondering whether there is a way to fetch data already written in DDR3 from this module and put it at the head of JESD204 (feeding it to the JESD204 module).
Is it possible or a way to do it? I was thinking to AXI_DMA but I am not sure where it is the solution or not.
Any help and guide are in advance appreciated.
Bests,