AbinayaSivam
Member level 1
My normal counter code
I am trying to implement the above code in Quartus and NIOS.
counter's clock speed is 50MHz, So counter data is missing in NIOS console.
So i need to give control to FIFO (write signal) through VERILOG.
I need to change my counter design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full. Please suggest me ,
Code:
module counter
(
input clk, enable, rst_n,
output reg[31:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule
I am trying to implement the above code in Quartus and NIOS.
counter's clock speed is 50MHz, So counter data is missing in NIOS console.
So i need to give control to FIFO (write signal) through VERILOG.
I need to change my counter design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full. Please suggest me ,