manjunath_crl
Newbie level 2
Dear Sir,
I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.
I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.