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Jitter Margin in CPU Timing Closure, up to 80ps, too much? Unrealistic? Unecessary wa

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Mister_hass

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Hi all,

Jitter used to be a topic of high importance in CPUs in the 90ies and 2000, then it became silenced for the last 10 years.
Today's 2.5GHz PLLs jitter is less than 1ps-RMS correspondiing to 15 sigma of 15ps. Surprisingly people still close timings in CPU design using up to 80ps margin. Knowing that skews are less than 10ps, then why up to 70 ps is still allocated to jitter tolerance margin?
Can anyone confirm these numbers and why they are still in use.
Many thanks
 

Hi,

I have no experience with jitter combined with CPUs.

But the values seem to be very low.
Some time ago (maybe still today) they activly introduced jitter to the clock source.
They called it "spread spectrum" technology.
This was made to reduce the (narrow and) high EMI peaks...to comply with EMI regulations.

Thus I wonder about the given values.

Klaus
 

Mister_hass said:
Hi all,

Jitter used to be a topic of high importance in CPUs in the 90ies and 2000, then it became silenced for the last 10 years.
Today's 2.5GHz PLLs jitter is less than 1ps-RMS correspondiing to 15 sigma of 15ps. Surprisingly people still close timings in CPU design using up to 80ps margin. Knowing that skews are less than 10ps, then why up to 70 ps is still allocated to jitter tolerance margin?
Can anyone confirm these numbers and why they are still in use.
Many thanks
Click to expand...

These numbers seem absurd. Some of the equipment I have in my lab can generate GHz clock with picosend precision, embedded PLLs can do the same. Are you confused about jitter and clock skew perhaps?
 

Thanks for the reply,

I agree with your statements, PLLs are less than 1ps jitter, then why pick such an overkill 80ps margin for Jitter in closing timings at CPU design? Is 80ps margin still up to date? that's another question. Inputs I got from some SOC design colleagues seem to confirm

Thanks

ThisIsNotSam said:
These numbers seem absurd. Some of the equipment I have in my lab can generate GHz clock with picosend precision, embedded PLLs can do the same. Are you confused about jitter and clock skew perhaps?
Click to expand...
 

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