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30th August 2018, 07:22 #1
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lookup table implementation in verilog
how to store the following values in a lookup table (2 dimensional memory) which is connected at the output of 8 bit latch in verilog ??
values to be stored are 0.011,0.087,0.045,0.415

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30th August 2018, 08:01 #2
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Re: lookup table implementation in verilog
Hi,
I just see 4 floating point values....
How are they related to "8 bit"?
I can´t see "2 dimensional" nor can a floating point value fit into "8 bit"
> Please elaborate your question.
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30th August 2018, 09:36 #3
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Re: lookup table implementation in verilog
This is the figure i was talking about .
   Updated   
i'm doing a project on design of a low power logarithmic arithmetic unit . As you know logarithmic addition is complicated which is given by logb(x+y)=logbx+logb(1+b^(logbxlogby)) . so a lookup table is required for computing the 2nd part of the logarithmic addition function . if you carefully observe the figure which i posted in previous reply 
X and Y are two 8bit numbers .
sx=X[7]
sy=Y[7]
x=logX
y=logY
d is an 8 bit register
d=xy
d0 is the LSB bit which is used for enabling the latches . so in the figure shown , the 4 latches receive d[7:1]
Till this point i coded everything and i got the simulations perfectly . now 4 lookup tables should be connected at the output of 7 bit latches out of which
the first two represent addition function and the rest two represent subtraction function . I theoritically calculated the function values and obtained 0.0111,0.087,0.045,0.415 respectively . so , my doubt is how do i store these floating point numbers in a memory (lookup table) in verilog ? could you please help me out

30th August 2018, 09:58 #4
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Re: lookup table implementation in verilog
Hi,
still unclear where are the floating point numbers.
From the text I assume it is d, but d is an 8 bit value, which is not suitable for floating point.
Or are you talking about fixed point? Where and what format?
Btw: It´s not very usual to use floating point values in an FPGA  but not impossible if the application really needs it.
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30th August 2018, 10:50 #5
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Re: lookup table implementation in verilog
here i need to partition the lookup table based on sd0 which acts as enable . latches are used to freeze the address of lookup tables . At a time only 1 lookup table will be active . i have to connect 4 such LUT's to the latches . how to store these values in a memory in verilog 0.0111,0.087,0.045,0.415 respectively . can you give me the direct verilog syntax for this ?

30th August 2018, 15:13 #6
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Re: lookup table implementation in verilog
You can't store those value in 8bit vector.

30th August 2018, 16:32 #7
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Re: lookup table implementation in verilog
Then how can I store it ? Will you please tell me any other way

30th August 2018, 22:20 #8
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Re: lookup table implementation in verilog
There are many different ways of representing floating point numbers. Using 8 bits is not one of them. Do a search on IEEE 754 for one format.

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4th September 2018, 07:14 #9
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Floating point representation in Verilog
how to represent these numbers in verilog?
0.011,0.087,0.045,0.415

4th September 2018, 07:33 #10
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Re: lookup table implementation in verilog
Hi,
What new information are you wating for?
8 bit is impossible.
Thus:
* either choose a fixed point format (with your desired range and resolution. No one can do this for you)
* or choose a standard floating point format. (very common is the 32 bit binary format)
There are online calculators for decimal (float) to binary (float) and vice versa calculations.
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7th September 2018, 05:34 #11
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Re: lookup table implementation in verilog
hello i used combinational logic for implementing LUT by using case statements . whatever values i gave are not coming exactly in the simulation. only integer part is coming and fractional part is not comimng . for ex: 5.734 . my simulation is showing only 5 . how do i get the exact values ?

7th September 2018, 10:29 #12
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7th September 2018, 17:13 #13
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Re: lookup table implementation in verilog
you didnt get my question. there is nothing wrong in the design . by using case statements i only assigned outputs for corresponding inputs as 0.011,0.087,0.045,0.415 . but in the simulation all 0's are coming . do u know how to assign the above numbers in verilog ? please help me out . i got stuck here from so many days

7th September 2018, 18:09 #14
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Re: lookup table implementation in verilog
Hi,
i got stuck here from so many days
* Ignoring our posts about dataformat
* not showing your code / design
* not showing your simulation / simulation results
...
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

7th September 2018, 19:02 #15

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8th September 2018, 00:12 #16
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Re: lookup table implementation in verilog
If you are sure that your design is 100% correct try to contact with your's tool manufacturer.

8th September 2018, 00:30 #17
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Re: lookup table implementation in verilog
Design is obviously not 100% correct.
e.g.
Code Verilog  [expand] 1 2 3 4 5
wire [7:0] sig1; assign sig1 = 0.011; // always assigns 0 to sig1 as only the integer part is assigned wire [7:0] sig2; assign sig2 = 18.0235; // results in the value 8'b 0001_0010 (18  integer part) being assigned to sig2
As was already pointed out in previous replies: you can scale the values, use a fixed point format, or use some floating point format.
Given your track record you'll probably just ask how to assign your values again.
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