Anklon
Member level 1
I have a non- synthesized verilog code :
verilog code for moduleLogic is also given and lef file for module Macro too. after synthesizing, my verilog looks like this:
but I would like to have a synthesized verilog without any hierarchical module inside it. It would be great if instead of synthesizing moduleLogic module as a module inside the verilog code , genus include the synthesized instructions as a part of the module adc portion.
How can I do that ?
sidenote: we do not have licence for hierarchical Innovus license. So, I'm trying to avoid any hierarchical module synthesizing as long as possible.
thank you for your time.
Code:
module [B]adc[/B](...)
...
...
[B]moduleMacro[/B] instance_1 (...)
[B]moduleLogic[/B] instance_2 (...)
...
endmodule
verilog code for moduleLogic is also given and lef file for module Macro too. after synthesizing, my verilog looks like this:
Code:
module [B]moduleLogic[/B](...)
//synthesized form of this module
endmodule
module [B]adc[/B](...)
...
...
[B]Macro[/B] inst1 (...)
[B]moduleLogic[/B] inst2(...)
...
endmodule
but I would like to have a synthesized verilog without any hierarchical module inside it. It would be great if instead of synthesizing moduleLogic module as a module inside the verilog code , genus include the synthesized instructions as a part of the module adc portion.
How can I do that ?
sidenote: we do not have licence for hierarchical Innovus license. So, I'm trying to avoid any hierarchical module synthesizing as long as possible.
thank you for your time.