knoxknox
Newbie level 1
In dual-rail design, in a 2-inputs logic gates like an AND, the input signals have to be separated by a spacer '00' before calculating a new result with 2 others valid data (see figure 1, 2 and 3 here:https://pdfs.semanticscholar.org/f59e/f2b6f608c6928c45273a4439fb7cef1db384.pdf ).
Let's assume a dual-rail asynchronous circuit that takes at the input a normal 1-bit signal A. At first, the signal A needs to be converted into a dual-rail signal, that means decomposed into two signals A1=A and A0=not(A). Then, this signal A1A0 is used at the input of a dual-rail AND gate. However, as seen previously, data at the input of a dual-rail needs to alternate between valid (01 or 10) and invalid (00) code-words.
Which circuit can I use to alternate the value of my signal A between valid and not-valid data, while taking into account an external change of the value of A ?
Let's assume a dual-rail asynchronous circuit that takes at the input a normal 1-bit signal A. At first, the signal A needs to be converted into a dual-rail signal, that means decomposed into two signals A1=A and A0=not(A). Then, this signal A1A0 is used at the input of a dual-rail AND gate. However, as seen previously, data at the input of a dual-rail needs to alternate between valid (01 or 10) and invalid (00) code-words.
Which circuit can I use to alternate the value of my signal A between valid and not-valid data, while taking into account an external change of the value of A ?