Inversion coefficient methodology

Hi,
I have read various posts on inversion coefficient and technology current.
I guess that the technology current may need to be changed as L changes.

In my design, I have opted for fixed L = 1 u
This reduces Short channel effects and eliminates one design step in IC based design.

To determine Ispec or Io , technology current, I have referred "Minimum Power in Analog Amplifying Blocks: Presenting a Design Procedure"
https://ieeexplore.ieee.org/document/7336662/

I obtained a range of tech current for NMOS and PMOS
for W/L = 1u/1u at T=27 C

NMOS Tech current ~900nA
PMOS Tech current ~300nA

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The Design Procedure

For the NMOS input differential difference amplifier (DDA) , I chose the transistors at the folding point (carrying 30uA) to be in Strong Inversion.

This is the part which is not clear, implementing on tool
IC Method: Choose inversion level (IC) and then, from drain current choose W (L has been fixed to 1u)
IC > 10 Id = 30uA Io = 300nA ~ 400nA W < 10
W = 8u (say)
choose Vov


Potential Distribution Methodology: Keep Vov > 200mV and then choose W for 30uA


Firstly, what is the difference?
Does IC mehtodology helps only in making the design technology independent?

For BSIM 3v3 models, is gm/Id seems appropriate indicator of inversion level
For the technology currents mentioned above, the gm/Id VS IC curve starts bending downwards near IC ~2.