dipin
Full Member level 4
hi,
i had some 40 nos of 32 bit constant in a verilog module used for some calculations. i am replicating this module for some 10 times.
so basically i am repeating the values in all the modules and wasting resources. so is it possible to declare it only once and use it in all the 10 modules.
10 instantiations are from the same module.
i declared it like this.
how can i do it? if it do so will it reduce the logic utilization?
any help is really appriciated
thanks and regards
i had some 40 nos of 32 bit constant in a verilog module used for some calculations. i am replicating this module for some 10 times.
so basically i am repeating the values in all the modules and wasting resources. so is it possible to declare it only once and use it in all the 10 modules.
10 instantiations are from the same module.
i declared it like this.
so instead of repeating like this in all modules is it possible to declare only once and use it in all the 10 modules?reg [15:0] mem [0:40];
how can i do it? if it do so will it reduce the logic utilization?
any help is really appriciated
thanks and regards