msdarvishi
Full Member level 4
Dear all,
I have a question that I would sincerely appreciate if someone can provide me a good and resonable definition of that.
We know that we can extract the critical paths in any FPGA design.
My question is that: "What is the difference between "Standard Path Delays" and "Critical Path Delays" in an FPGA design??
Kind replies and help are in advance appreciated.
Regards,
I have a question that I would sincerely appreciate if someone can provide me a good and resonable definition of that.
We know that we can extract the critical paths in any FPGA design.
My question is that: "What is the difference between "Standard Path Delays" and "Critical Path Delays" in an FPGA design??
Kind replies and help are in advance appreciated.
Regards,