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    Write a verilog/system verilog of a normally open momentary switch toggle with delays

    How to write in verilog and/or system verilog a normally open switch with delays with the following functionality: when pressed once it outputs 1 and stays 1 when depressed, when pressed a second time it outputs 0 and stays 0 when depressed. The 1 output is instantaneous upon pressing, the 0 output only occurs if the button is pressed for a determined time. This is essentially how the power button in desktops work: if computer is off pressing the button starts the computer but, if the computer is on, the button requires to be pressed for several seconds.

    •   Alt10th January 2018, 01:31

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    Re: Write a verilog/system verilog of a normally open momentary switch toggle with de

    Is it a Verilog software exercise or a hardware design? In the latter case, you need a clock to implement the delay timer and key debouncing.

    A PC realizes the respective function in the BIOS firmware. You probably noticed that the off-delay becomes effective after the operation system has booted, you have a fast turn-off function during initial boot phase.


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    •   Alt10th January 2018, 07:55

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  3. #3
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    Re: Write a verilog/system verilog of a normally open momentary switch toggle with de

    Quote Originally Posted by cesarxhc View Post
    How to write in verilog and/or system verilog a normally open switch with delays with the following functionality: when pressed once it outputs 1 and stays 1 when depressed, when pressed a second time it outputs 0 and stays 0 when depressed. The 1 output is instantaneous upon pressing, the 0 output only occurs if the button is pressed for a determined time. This is essentially how the power button in desktops work: if computer is off pressing the button starts the computer but, if the computer is on, the button requires to be pressed for several seconds.
    Hello,

    as more experienced colleague has written you need: clok, counter (timer), debouncer (for button/switch) and very simple "state machine"( the state machine is for remember the actual state of switch) components. Just find out how to implement these components in Verilog (Google) and then interconnect them all in your project.

    Regards



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