r1caw ex ua6bqg
Member level 2
Hi all!
During CTS stage in Synopsys ICC I observed the .log file and found some information about technology-based delay scale factors (see .log below):
Technology-based gate delay scale factors (normalized to the highest):
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 0.644
Corner 'TEST_ML:max': 0.457
Corner 'TEST_BC:max': 0.450
Corner 'T1:max': 0.551
Corner 'ML:max': 0.457
Corner 'BC:max': 0.450
Corner 'WC:max': 0.865
Technology-based wire delay scale factors (normalized to the highest):
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 1.000
Corner 'TEST_ML:max': 1.000
Corner 'TEST_BC:max': 1.000
Corner 'T1:max': 1.000
Corner 'ML:max': 1.000
Corner 'BC:max': 1.000
Corner 'WC:max': 1.000
Using the following scale factors for float pins:
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 0.716
Corner 'TEST_ML:max': 0.566
Corner 'TEST_BC:max': 0.560
Corner 'T1:max': 0.641
Corner 'ML:max': 0.566
Corner 'BC:max': 0.560
Corner 'WC:max': 0.892
Worst clock corner: :max
Worst RC delay corner: :max
Using normal effort optimization
I use all necessary technology files for CTS (i.e. TLU+, etc), and the main question is why wire-delay scale factor is constant (1.0)? Why it cannot changes like, for example, logical gates?
During CTS stage in Synopsys ICC I observed the .log file and found some information about technology-based delay scale factors (see .log below):
Technology-based gate delay scale factors (normalized to the highest):
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 0.644
Corner 'TEST_ML:max': 0.457
Corner 'TEST_BC:max': 0.450
Corner 'T1:max': 0.551
Corner 'ML:max': 0.457
Corner 'BC:max': 0.450
Corner 'WC:max': 0.865
Technology-based wire delay scale factors (normalized to the highest):
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 1.000
Corner 'TEST_ML:max': 1.000
Corner 'TEST_BC:max': 1.000
Corner 'T1:max': 1.000
Corner 'ML:max': 1.000
Corner 'BC:max': 1.000
Corner 'WC:max': 1.000
Using the following scale factors for float pins:
Corner ':max': 1.000
Corner 'WL:min': 1.000
Corner 'TEST_TY:max': 0.716
Corner 'TEST_ML:max': 0.566
Corner 'TEST_BC:max': 0.560
Corner 'T1:max': 0.641
Corner 'ML:max': 0.566
Corner 'BC:max': 0.560
Corner 'WC:max': 0.892
Worst clock corner: :max
Worst RC delay corner: :max
Using normal effort optimization
I use all necessary technology files for CTS (i.e. TLU+, etc), and the main question is why wire-delay scale factor is constant (1.0)? Why it cannot changes like, for example, logical gates?