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Newbie level 3
Hi
I understand that it is possible to force a signal at compile time (with NCSIM at least) so that it will have a constant value every simulation without the need for run-time intervention. However, I can't seem to find any documentation for this on Google.
Note I would rather not modify the RTL code since this is configuration-dependent and for testing purposes only (not synthesis).
Is this possible? Ideally I would want to do the same in VCS as well.
Many thanks
I understand that it is possible to force a signal at compile time (with NCSIM at least) so that it will have a constant value every simulation without the need for run-time intervention. However, I can't seem to find any documentation for this on Google.
Note I would rather not modify the RTL code since this is configuration-dependent and for testing purposes only (not synthesis).
Is this possible? Ideally I would want to do the same in VCS as well.
Many thanks