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  1. #1
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    Verilog Assignment code

    Hi All,
    Please anyone tell me how the below code works?

    Code Verilog - [expand]
    1
    
    assign  Reset = (a & cnt[19])? (ok_cnt[19]? b: 1'b1) : b;

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  2. #2
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    Re: Verilog Assignment code

    Reset is assigned based on the conditions on the RHS.

    ? is the conditional operator in verilog:
    (condition) ? (value when condition_is_true) : (value when condition_is_false);

    Remember in verilog, like C, any non-zero value counts as true.

    - - - Updated - - -

    Btw - google will get you many Verilog tutorials - here is the first hit for me:
    http://www.asic-world.com/verilog/veritut.html



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  3. #3
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    Re: Verilog Assignment code

    can you please convert the above code into vhdl?



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  4. #4
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    Re: Verilog Assignment code

    Quote Originally Posted by hareeshP View Post
    can you please convert the above code into vhdl?
    Following through the Verilog tutorials should mean you could do this yourself.



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    Re: Verilog Assignment code

    actually i am following the vhdl tutorial and i wants convert a verilog source code into vhdl one. So i need to understand the logic used in verilog.



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