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Approaches for a complete verification

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rprince006

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Hi verification guys,

As every body knows, functional verification is a difficult task, and there is no
industry standard flows/tools in the field. Most ASIC companies have their own approaches, and most of them are combinations of several the state of the art
flows/tools. Presently, we are using tranditional HDL/C testbench based flow, to
cover most direct tests, and using specman/e to cover some difficult random
tests, also using formal methods only for a thorough module level tests.

Could you guys please talk about the approach you are using for functional verification for complex systems?

Many thanks!

Regards,
rprince006,
 

If you have access to the powerful verification automation features provided by specman elite, why you still need HDL/C testbench?

I use python together with the package myhdl as the HVL. It's powerful and free. I use PSL as the assertion language for temporal checking and functional coverage group/point definition.

The problem I have is that I don't have a good constraint solver with python yet.
 

Hi Arnold,

Because we are on a big project of verifying a complex system, we
have to re-use some of our verification effort. The HDL testbench was
built mainly for direct tests, and it was immigrated from other project.
HDL-based testbench is still the best way for direct tests, though it is
time-consuming to build.

Specman is quite powerful for random tests, and it has a powerful contraint
solver. But it is expensive, and not so easy to use, because it is not easier
to find e reference compared to Verilog and VHDL, which are already industry
standard language.

I have no idea about the HVL languages you have mentioned. Would you
please talk more about them?

Regards,
 

For the last three chips( all is over 7 million gates), we use vera to construct testbench and reference model.
 

hi,

you can verify design using hvls like e-lang,vera,psl/sugar,systemverilog.

with regards,
kul.
 

i use verilog + psl, specman is too expensive
 

we use fpga system to verify our asic chips,

when we find bug, then simulation is run to find and eliminate bug.

rprince006 said:
Hi verification guys,

As every body knows, functional verification is a difficult task, and there is no
industry standard flows/tools in the field. Most ASIC companies have their own approaches, and most of them are combinations of several the state of the art
flows/tools. Presently, we are using tranditional HDL/C testbench based flow, to
cover most direct tests, and using specman/e to cover some difficult random
tests, also using formal methods only for a thorough module level tests.

Could you guys please talk about the approach you are using for functional verification for complex systems?

Many thanks!

Regards,
rprince006,
Click to expand...
 

hi
if you have an HVL like specman your entire test bench shopuld be made in it??
when you use any HVL you can take advantage of functional coverage. this will give u a very good idea how much you have actually verified. when you achieve a good coverage percentage (say >90) you can be very confident about your design. but usage of functional coverage calls for an extensive state space identification and state space reduction before you start developing.
 

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