inputoutput
Member level 1
I have finished synthesizing my circuit in design compiler. Now I want to do a gate level simulation in Modelsim in order to get the power consumption. The gate level simulation works correctly, but generates "xxx" when annotated with the SDF generated by design compiler. I've tried to reduce the clock frequency but still get the same result. I should add that I've specified input and output delays to the ports (using
and
DC commands) during synthesis, could this be in any way related? Any thoughts?
HTML:
set_input_delay
HTML:
set_output_delay