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FFT core design on FPGA board

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mohamed_shfat

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Greetings all
I'm here new to the FPGA world and the HDL as well, i'm trying to implement some FFT core function on my Arty 7 FPGA board used the verilog language, but unfortunately i'm facing a lot of problems to control this core and make it work successfully.
My question here is about the data_valid line of the input of the FFT core v9.0 , how can i design or control this line with a good way so it allows the data to be streamed to the core. Can I for example make it always high data_valid =1 because i'm using a real time processor and getting the data from the XADC, or there is another way? Or is there any ready state machine design to control this FFT core?
Please if someone can help me i would really appreciate the help too much.
Regards
Mohamed
 


Hi,

I don´t have experience with this core. But there should be a documentiation for this core. Read it.

***
Generally:
FFT is some kind of block procesing.
It usually has a fixed "depth" (2^n, in your case maybe 1024)....This means you need to input 1024 datasets, then start the processing of all the data.

*****
You are new to FPGA.. I don´t think it´s a good idea to start with an FFT on the FPGA.
Start with simple things.
Get familiar with the language, get familiar with the software tools and with the FPGA and it´s features.

Klaus
 

FFT and FIFO synchronization in FPGA

Greetings everyone
Can anyone please help me and tell me how can I use the FIFO memory IP CORE to synchronize and control my FFT core.
Recently I did a small research about controlling the FFT IP CORE v9.0 and I found many users who has used the FIFO as a useful tool for that. But unfortunately I couldn't get the full idea especially that this still my first project on FPGA field.
Please if anyone can help me for this point i would really appreciate the help.
Muhamed
 

You probably should start define the signal processing problem more clearly.

Input data rate, intended FFT block size, windowing required, block overlapping? What's the FFT data sink?
 

Hi,

Yes. I really wonder how some people design their applications. Completely without specifications?
The OP is one of many who claims that something doesn't work like expected, but gives not a single specification about it's operation.

And an FFT surely needs a lot of specifications. Data format and data width, I/O timings, processing time...

It's a pity, without those informations...we are not able to help..

Klaus
 

First thanks for your reply sir :wink:
My question here was just about a part of my design which the best way to connect the asynchronous FIFO with FFT core. I asked if someone had an idea or did it before may help me to do it and tell me how it can be done perfectly.
Regards
 

My question here was just about a part of my design which the best way to connect the asynchronous FIFO with FFT core. I asked if someone had an idea or did it before may help me to do it and tell me how it can be done perfectly.
Click to expand...
The answer is, it depends on what you want to achieve with the FIFO.
Connecting a FIFO to the FFT streaming interface is simple and straightforward. But it's not the whole application.
 

Hi,

I have used FFT with FIFO and i have used FFT without FIFO.
FIFO can be in input, in output or both.

Klaus
 

KlausST said:
Hi,

I have used FFT with FIFO and i have used FFT without FIFO.
FIFO can be in input, in output or both.

Klaus
Click to expand...

Ok sir, may you please just tell me how can i use it at the input of the FFT, can use AXI Stream for FIFO and connect the handshake ports (Ready - Valid) directly to the FFT's handshake input ports or not.
Thanks for everything
 

FvM said:
The answer is, it depends on what you want to achieve with the FIFO.
Connecting a FIFO to the FFT streaming interface is simple and straightforward. But it's not the whole application.
Click to expand...

Thanks for the reply sir
I want to achieve the best correct data streaming and controlling the FFT core, may you please explain me how can i connect the FFT and FIFO streaming interface easly. And thanks too much
 

Hi,

Where is the problem in connecting datalines?
And maybe you need to write some logic for the "FIFO to FFT" control lines....and your overall timing.

I have no experience with AXI, but it seems to be memory mapped. Therefore you need an address decoder to find out wich data belong to the FIFO.


Klaus
 

You didn't mention in #1 that you would like to know how to use a FIFO and FFT core in conjugation.

Well 1st question, have you read the Xilinx documentation on how to generate and use a FIFO?
If you know how to use a FIFO it is just trivial to connect it to the FFT core!
 

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