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Process variations that results from transistor size

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gunturikishore

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Hi everybody,

Please help me in this problem. Can any body say how much variation I can expect that the process techniques vary in designed width and length of transisotrs. I had verysamll transistors of width 1.3u NMOS and 3.4u PMOS devices on .18u technology used to make the inverters which have to drive transistors of 120 u at the GATE . How much variations I can expect in the size of the above transistors

Thanks in advance.
 

Re: Process variations

Dear Kishore,

The worst case varaiations in any process for most of the parameters is ± 10 %. Usually foundries deem only those processes as stable and would work with them.
 

Re: Process variations

Look for the data provided by the foundry on mismatch parameters.
It would memtion what variations to expect when 2 transistors are placed close to each other. Distance of saperation is also specified by the foundry.
 

Process variations

as far as i know for a design is expected to work properly if during simulations it gives proper functionality for ± 20 % variations in process parameters. but as vamsi said the foundaries consider only those processes as stable which give a variation of ± 10 %
 

Re: Process variations

I think the model provided by foundry has enough information. You can simulate all the case (TT, FF, SS) combined with VDD variation. If all pass, I think it's enough.

Yibin
 

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