gunturikishore
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Hi everybody,
Please help me in this problem. Can any body say how much variation I can expect that the process techniques vary in designed width and length of transisotrs. I had verysamll transistors of width 1.3u NMOS and 3.4u PMOS devices on .18u technology used to make the inverters which have to drive transistors of 120 u at the GATE . How much variations I can expect in the size of the above transistors
Thanks in advance.
Please help me in this problem. Can any body say how much variation I can expect that the process techniques vary in designed width and length of transisotrs. I had verysamll transistors of width 1.3u NMOS and 3.4u PMOS devices on .18u technology used to make the inverters which have to drive transistors of 120 u at the GATE . How much variations I can expect in the size of the above transistors
Thanks in advance.