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Design considerations for having pulse train frequency with the same speed as clock

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no_mad

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hi all,

In a design with single clocking scheme and the output is a pulse train. The challenge is the pulse train frequency is same speed with the main clock (the only clock).

Based on ur experience, can I registered (flop) my output signal? As far as I know, I can’t do that since it has the same speed with the main clock. Can I use frequency multiplier to double my main clock so that I can clocked my output flop?

If yes, what are the design considerations which I need to take care?

Please give me your opinion.

Thanx in advance,
no_mad
 

Re: Design opinion

You have signal at the same frequency as the clk. So now you want to latch the this signal. Consider the case that your signal is reaches the FF(flipflop) input before its Setup time and remain the same till its holdtime then you can practically latch this.. You can do this by introducing some phase difference betwen the signal clk and main clk...
 

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