ruwan2
Member level 5
Hello,
I wrote some Verilog code a long time ago. Now I get some VCD code as below. I find some lines cannot be understood, such as:
I guess that the above question could be resulted from below:
$var wire 1 aaaaa A $end
Does it say a 5-bit signal?
'x' at the beginning means undetermined value?
Can you explain it to me above?
Thanks,
-----------------
I wrote some Verilog code a long time ago. Now I get some VCD code as below. I find some lines cannot be understood, such as:
Code dot - [expand] 1 2 3 4 5 6 7 8 9 10$dumpvars xaaaaa xaaaab xaaaac xaaaad $end #1 1aaaaa
I guess that the above question could be resulted from below:
$var wire 1 aaaaa A $end
Does it say a 5-bit signal?
'x' at the beginning means undetermined value?
Can you explain it to me above?
Thanks,
-----------------
Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 $date Dec 24, 2016 16:54:43 $end $version SystemC 2.3.1-Accellera --- Dec 22 2016 15:46:30 $end $timescale 1 ps $end $scope module SystemC $end $var wire 1 aaaaa A $end $var wire 1 aaaab B $end $var wire 1 aaaac C $end $var wire 1 aaaad D $end $upscope $end $enddefinitions $end $comment All initial values are dumped below at time 0 sec = 0 timescale units. $end $dumpvars xaaaaa xaaaab xaaaac xaaaad $end #0 0aaaaa 1aaaab 0aaaac 1aaaad #1 1aaaaa #2 0aaaaa 0aaaab 1aaaac 0aaaad #3 1aaaaa
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