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  1. #1
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    Issue the FIFO implementation

    HI.

    Now I'm trying to implement the xilinx fifo into my FPGA as below.
    Click image for larger version. 

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    But I think the FIFO does not work. I just make it where from Coregen of ISE tool.
    fifo1.v
    Code:
    `timescale 1ns/1ps
    
    module fifo1(
      rst,
      wr_clk,
      rd_clk,
      din,
      wr_en,
      rd_en,
      dout,
      full,
      almost_full,
      wr_ack,
      overflow,
      empty,
      almost_empty,
      valid,
      underflow,
      rd_data_count,
      wr_data_count
    );
    
    input rst;
    input wr_clk;
    input rd_clk;
    input [7 : 0] din;
    input wr_en;
    input rd_en;
    output [7 : 0] dout;
    output full;
    output almost_full;
    output wr_ack;
    output overflow;
    output empty;
    output almost_empty;
    output valid;
    output underflow;
    output [13 : 0] rd_data_count;
    output [13 : 0] wr_data_count;
    
    // synthesis translate_off
    
      FIFO_GENERATOR_V9_3 #(
        .C_ADD_NGC_CONSTRAINT(0),
        .C_APPLICATION_TYPE_AXIS(0),
        .C_APPLICATION_TYPE_RACH(0),
        .C_APPLICATION_TYPE_RDCH(0),
        .C_APPLICATION_TYPE_WACH(0),
        .C_APPLICATION_TYPE_WDCH(0),
        .C_APPLICATION_TYPE_WRCH(0),
        .C_AXI_ADDR_WIDTH(32),
        .C_AXI_ARUSER_WIDTH(1),
        .C_AXI_AWUSER_WIDTH(1),
        .C_AXI_BUSER_WIDTH(1),
        .C_AXI_DATA_WIDTH(64),
        .C_AXI_ID_WIDTH(4),
        .C_AXI_RUSER_WIDTH(1),
        .C_AXI_TYPE(0),
        .C_AXI_WUSER_WIDTH(1),
        .C_AXIS_TDATA_WIDTH(64),
        .C_AXIS_TDEST_WIDTH(4),
        .C_AXIS_TID_WIDTH(8),
        .C_AXIS_TKEEP_WIDTH(4),
        .C_AXIS_TSTRB_WIDTH(4),
        .C_AXIS_TUSER_WIDTH(4),
        .C_AXIS_TYPE(0),
        .C_COMMON_CLOCK(0),
        .C_COUNT_TYPE(0),
        .C_DATA_COUNT_WIDTH(14),
        .C_DEFAULT_VALUE("BlankString"),
        .C_DIN_WIDTH(8),
        .C_DIN_WIDTH_AXIS(1),
        .C_DIN_WIDTH_RACH(32),
        .C_DIN_WIDTH_RDCH(64),
        .C_DIN_WIDTH_WACH(32),
        .C_DIN_WIDTH_WDCH(64),
        .C_DIN_WIDTH_WRCH(2),
        .C_DOUT_RST_VAL("0"),
        .C_DOUT_WIDTH(8),
        .C_ENABLE_RLOCS(0),
        .C_ENABLE_RST_SYNC(1),
        .C_ERROR_INJECTION_TYPE(0),
        .C_ERROR_INJECTION_TYPE_AXIS(0),
        .C_ERROR_INJECTION_TYPE_RACH(0),
        .C_ERROR_INJECTION_TYPE_RDCH(0),
        .C_ERROR_INJECTION_TYPE_WACH(0),
        .C_ERROR_INJECTION_TYPE_WDCH(0),
        .C_ERROR_INJECTION_TYPE_WRCH(0),
        .C_FAMILY("virtex5"),
        .C_FULL_FLAGS_RST_VAL(1),
        .C_HAS_ALMOST_EMPTY(1),
        .C_HAS_ALMOST_FULL(1),
        .C_HAS_AXI_ARUSER(0),
        .C_HAS_AXI_AWUSER(0),
        .C_HAS_AXI_BUSER(0),
        .C_HAS_AXI_RD_CHANNEL(0),
        .C_HAS_AXI_RUSER(0),
        .C_HAS_AXI_WR_CHANNEL(0),
        .C_HAS_AXI_WUSER(0),
        .C_HAS_AXIS_TDATA(0),
        .C_HAS_AXIS_TDEST(0),
        .C_HAS_AXIS_TID(0),
        .C_HAS_AXIS_TKEEP(0),
        .C_HAS_AXIS_TLAST(0),
        .C_HAS_AXIS_TREADY(1),
        .C_HAS_AXIS_TSTRB(0),
        .C_HAS_AXIS_TUSER(0),
        .C_HAS_BACKUP(0),
        .C_HAS_DATA_COUNT(0),
        .C_HAS_DATA_COUNTS_AXIS(0),
        .C_HAS_DATA_COUNTS_RACH(0),
        .C_HAS_DATA_COUNTS_RDCH(0),
        .C_HAS_DATA_COUNTS_WACH(0),
        .C_HAS_DATA_COUNTS_WDCH(0),
        .C_HAS_DATA_COUNTS_WRCH(0),
        .C_HAS_INT_CLK(0),
        .C_HAS_MASTER_CE(0),
        .C_HAS_MEMINIT_FILE(0),
        .C_HAS_OVERFLOW(1),
        .C_HAS_PROG_FLAGS_AXIS(0),
        .C_HAS_PROG_FLAGS_RACH(0),
        .C_HAS_PROG_FLAGS_RDCH(0),
        .C_HAS_PROG_FLAGS_WACH(0),
        .C_HAS_PROG_FLAGS_WDCH(0),
        .C_HAS_PROG_FLAGS_WRCH(0),
        .C_HAS_RD_DATA_COUNT(1),
        .C_HAS_RD_RST(0),
        .C_HAS_RST(1),
        .C_HAS_SLAVE_CE(0),
        .C_HAS_SRST(0),
        .C_HAS_UNDERFLOW(1),
        .C_HAS_VALID(1),
        .C_HAS_WR_ACK(1),
        .C_HAS_WR_DATA_COUNT(1),
        .C_HAS_WR_RST(0),
        .C_IMPLEMENTATION_TYPE(2),
        .C_IMPLEMENTATION_TYPE_AXIS(1),
        .C_IMPLEMENTATION_TYPE_RACH(1),
        .C_IMPLEMENTATION_TYPE_RDCH(1),
        .C_IMPLEMENTATION_TYPE_WACH(1),
        .C_IMPLEMENTATION_TYPE_WDCH(1),
        .C_IMPLEMENTATION_TYPE_WRCH(1),
        .C_INIT_WR_PNTR_VAL(0),
        .C_INTERFACE_TYPE(0),
        .C_MEMORY_TYPE(1),
        .C_MIF_FILE_NAME("BlankString"),
        .C_MSGON_VAL(1),
        .C_OPTIMIZATION_MODE(0),
        .C_OVERFLOW_LOW(0),
        .C_PRELOAD_LATENCY(1),
        .C_PRELOAD_REGS(0),
        .C_PRIM_FIFO_TYPE("8kx4"),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
        .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
        .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
        .C_PROG_EMPTY_TYPE(0),
        .C_PROG_EMPTY_TYPE_AXIS(0),
        .C_PROG_EMPTY_TYPE_RACH(0),
        .C_PROG_EMPTY_TYPE_RDCH(0),
        .C_PROG_EMPTY_TYPE_WACH(0),
        .C_PROG_EMPTY_TYPE_WDCH(0),
        .C_PROG_EMPTY_TYPE_WRCH(0),
        .C_PROG_FULL_THRESH_ASSERT_VAL(16381),
        .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
        .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
        .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
        .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
        .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
        .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
        .C_PROG_FULL_THRESH_NEGATE_VAL(16380),
        .C_PROG_FULL_TYPE(0),
        .C_PROG_FULL_TYPE_AXIS(0),
        .C_PROG_FULL_TYPE_RACH(0),
        .C_PROG_FULL_TYPE_RDCH(0),
        .C_PROG_FULL_TYPE_WACH(0),
        .C_PROG_FULL_TYPE_WDCH(0),
        .C_PROG_FULL_TYPE_WRCH(0),
        .C_RACH_TYPE(0),
        .C_RD_DATA_COUNT_WIDTH(14),
        .C_RD_DEPTH(16384),
        .C_RD_FREQ(1),
        .C_RD_PNTR_WIDTH(14),
        .C_RDCH_TYPE(0),
        .C_REG_SLICE_MODE_AXIS(0),
        .C_REG_SLICE_MODE_RACH(0),
        .C_REG_SLICE_MODE_RDCH(0),
        .C_REG_SLICE_MODE_WACH(0),
        .C_REG_SLICE_MODE_WDCH(0),
        .C_REG_SLICE_MODE_WRCH(0),
        .C_SYNCHRONIZER_STAGE(2),
        .C_UNDERFLOW_LOW(0),
        .C_USE_COMMON_OVERFLOW(0),
        .C_USE_COMMON_UNDERFLOW(0),
        .C_USE_DEFAULT_SETTINGS(0),
        .C_USE_DOUT_RST(1),
        .C_USE_ECC(0),
        .C_USE_ECC_AXIS(0),
    and I use as below by instance.

    Code:
    d
    
            default:;
            endcase
    end
    
    //////////////////////////////////////////
    assign rd_clk = clk_99;
    
    fifo1 u_fifo1(
     .rst		( areset_n	),
     .wr_clk	( wr_clk	),
     .rd_clk	( rd_clk	),
     .din		(v2_dout          	),
    // .wr_en		( ((!full)&v2_hsync)&( c_v_st==  ST_V_START)   	),
     .wr_en		( ((!full)&v2_hsync)   	),
     .rd_en		( (!empty)        	),
                                       
     .dout		(dout1         	),
     .full		(full         	),
     .almost_full	(almost_full  	),
     .wr_ack	(wr_ack       	),
     .overflow	(overflow     	),
     .empty		(empty        	),
     .almost_empty	(almost_empty 	),
     .valid		(valid        	),
     .underflow	(underflow    	),
     .rd_data_count	(rd_data_count	),
     .wr_data_count (wr_data_count	)
    );
    
    ...
    Is that right to implement fifo what I use fifo.xco?
    Would you please let me know what I am missing?
    What am I suppose to do?

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  2. #2
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    Re: Issue the FIFO implementation

    But I think the FIFO does not work.
    Would you please let me know what I am missing?
    What am I suppose to do?
    What is the exact problem you are facing?
    You have just given a part of your code from which it is difficult to tell what is the problem.
    FPGA enthusiast!



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  3. #3
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    Re: Issue the FIFO implementation

    I expect the answer what I used the processing method.



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  4. #4
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    Re: Issue the FIFO implementation

    I expect the answer what I used the processing method.
    I don't understand the above sentence.

    What you have shown is just an instillation of the fifo module, which LOOKS correct. If anything was wrong compiler would catch the error and report. I am assuming that the connecting signals are doing what they are supposed to do (since no info are given on them)!

    Again...
    But I think the FIFO does not work.
    You THINK it does not work?
    Then show us the proof that it is not working via simu screen-shots. Show the clks, resets, rd_en, wr_en, etc............else how can anyone say whats wrong?

    1> Is the FIFO clocked and reset?
    2> Are you using a proper test-bench to drive/monitor the FIFO signals?

    -----------------------------------------------------
    btw - On a side note the following was another thread from 'coshy' on FIFO (which apparent wasn't solved):
    https://www.edaboard.com/thread359024.html
    Last edited by dpaul; 14th December 2016 at 11:07.
    FPGA enthusiast!



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