FIFO can't instance in synplify

[coshy]

Hi.

I've some problem when i use Xilinx's FIFO instance in the Synplify as below picture.



The u_pll33to100 is also Xilinx's PLL module but it was instanced as well in the Synplify.
I can't understand especially why does only fifo not instanced in Synplify.

How do I supposed to do for solving this problem?

 

[ads-ee]

I have no clue what your question is. What do you men by instanced in Synplify?

Synplify is a synthesis tool it doesn't instance submodules.

Based on what you've shown there is nothing wrong.

 

[coshy]

I have no clue what your question is. What do you men by instanced in Synplify?

Synplify is a synthesis tool it doesn't instance submodules.

Based on what you've shown there is nothing wrong.

Don't you see that difference between pll and fifo?
Pll has a lot of instance but fifo doesnt.

 

[TrickyDicky]

Don't you see that difference between pll and fifo?
Pll has a lot of instance but fifo doesnt.

I see one PLL and 1 FIFO. Whats the issue?
The number of PLL and FIFOs will be down to your code, no the compiler.

 

[coshy]

I see one PLL and 1 FIFO. Whats the issue?
The number of PLL and FIFOs will be down to your code, no the compiler.

Yes, you are right. But you can see also some differences which are u_pll33to100 has some instance such as PLL_ADV_INST, ..., and CLKIN1_IBUFG_INST. But u_fifo_generator has nothing. As I know u_fifo_generator_v9_3 has some instance module such as FIFO_GENERATOR_V9_3.. but in this case, I can't see these instances.

 

[FvM]

As far as I understand, coshy is wondering why the PLL module instantiates submodules and the FIFO module does not.

Without looking into the design files, this seems to me an almost useless question. Possible reasons can be
- the generated code simply does not use submodules
- it's instantiating protected IP which is hidden in the RTL hierarchy view, because the respective sources can't be opened

If you have any indications that the FIFO module isn't synthesized in your design (e.g. because essential connections are missing), you should tell.

 

[coshy]

As far as I understand, coshy is wondering why the PLL module instantiates submodules and the FIFO module does not.

Without looking into the design files, this seems to me an almost useless question. Possible reasons can be
- the generated code simply does not use submodules
- it's instantiating protected IP which is hidden in the RTL hierarchy view, because the respective sources can't be opened

If you have any indications that the FIFO module isn't synthesized in your design (e.g. because essential connections are missing), you should tell.

I think you can understand what I'm saying as below picture.



and I've upload my code.

module test1( 
...
);

 pll33to100 u_pll33to100(
 				.CLKIN1_IN	(aclk		),
 				.RST_IN		(!rst	),
                .CLKOUT0_OUT(clk_99	), 
                .CLKOUT1_OUT(clk_24	), 
                .LOCKED_OUT	(lock	)
                );

assign pclk = clk_99;

 my_fifo_sy u_my_fifo_sy (
  .rst (!rst),
  .wr_clk (clk_24),
  .rd_clk (pclk),
  .din (data_out),
  .wr_en ( !slwr_w), //slwr_w ?
  .rd_en ( !empty ),
  .dout (dout),
  .full (full),
  .almost_full (),
  .wr_ack (wr_ack),
  .overflow (),
  .empty (empty),
  .almost_empty (),
  .valid (valid),
  .underflow (),
  .rd_data_count (rd_data_count),
  .wr_data_count (wr_data_count)
	);


slaveFIFO2b_streamIN stream_in_inst
	(
	 .reset_(rst),
         .clk_100(pclk),
...
         .data_out_stream_in(data_out)
	); 



...
endmodule

and

module pll33to100(CLKIN1_IN, 
                  RST_IN, 
                  CLKOUT0_OUT, 
                  CLKOUT1_OUT, 
                  LOCKED_OUT);

    input CLKIN1_IN;
    input RST_IN;
   output CLKOUT0_OUT;
   output CLKOUT1_OUT;
   output LOCKED_OUT;
   
   wire CLKFBOUT_CLKFBIN;
   wire CLKIN1_IBUFG;
   wire CLKOUT0_BUF;
   wire CLKOUT1_BUF;
   wire GND_BIT;
   wire [4:0] GND_BUS_5;
   wire [15:0] GND_BUS_16;
   wire VCC_BIT;
   
   assign GND_BIT = 0;
   assign GND_BUS_5 = 5'b00000;
   assign GND_BUS_16 = 16'b0000000000000000;
   assign VCC_BIT = 1;
   IBUFG  CLKIN1_IBUFG_INST (.I(CLKIN1_IN), 
                            .O(CLKIN1_IBUFG));
   BUFG  CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), 
                           .O(CLKOUT0_OUT));
   BUFG  CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), 
                           .O(CLKOUT1_OUT));
   PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(30.303), 
         .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(8), .CLKOUT1_DIVIDE(33), 
         .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), 
         .CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500), 
         .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), 
         .CLKFBOUT_MULT(24), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) 
         PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), 
                         .CLKINSEL(VCC_BIT), 
                         .CLKIN1(CLKIN1_IBUFG), 
                         .CLKIN2(GND_BIT), 
                         .DADDR(GND_BUS_5[4:0]), 
                         .DCLK(GND_BIT), 
                         .DEN(GND_BIT), 
                         .DI(GND_BUS_16[15:0]), 
                         .DWE(GND_BIT), 
                         .REL(GND_BIT), 
                         .RST(RST_IN), 
                         .CLKFBDCM(), 
                         .CLKFBOUT(CLKFBOUT_CLKFBIN),

module my_fifo_sy(
  rst,
  wr_clk,
  rd_clk,
  din,
  wr_en,
  rd_en,
  dout,
  full,
  almost_full,
  wr_ack,
  overflow,
  empty,
  almost_empty,
  valid,
  underflow,
  rd_data_count,
  wr_data_count
);

input rst;
input wr_clk;
input rd_clk;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [10 : 0] rd_data_count;
output [10 : 0] wr_data_count;

// synthesis translate_off

  FIFO_GENERATOR_V9_3 #(
    .C_ADD_NGC_CONSTRAINT(0),
    .C_APPLICATION_TYPE_AXIS(0),
    .C_APPLICATION_TYPE_RACH(0),
    .C_APPLICATION_TYPE_RDCH(0),
    .C_APPLICATION_TYPE_WACH(0),
    .C_APPLICATION_TYPE_WDCH(0),
    .C_APPLICATION_TYPE_WRCH(0),
    .C_AXI_ADDR_WIDTH(32),
    .C_AXI_ARUSER_WIDTH(1),
    .C_AXI_AWUSER_WIDTH(1),
    .C_AXI_BUSER_WIDTH(1),
    .C_AXI_DATA_WIDTH(64),
    .C_AXI_ID_WIDTH(4),
    .C_AXI_RUSER_WIDTH(1),
    .C_AXI_TYPE(0),
    .C_AXI_WUSER_WIDTH(1),
    .C_AXIS_TDATA_WIDTH(64),
    .C_AXIS_TDEST_WIDTH(4),
    .C_AXIS_TID_WIDTH(8),
    .C_AXIS_TKEEP_WIDTH(4),
    .C_AXIS_TSTRB_WIDTH(4),
    .C_AXIS_TUSER_WIDTH(4),

Did you find what I'm saying?
For example, the PLL has a lot of sub module instances but in the fifo case it doesn't.

 

[TrickyDicky]

Did you include the generated fifo core? Either the generated netlist or the source code.
Check the synth warnings:
Any warnings about a black box?

It may be that the netlist you generated is placed during the P&R - hence treated as a black box for synthesis (and no sub modules). Place and route can only be done in ISE/Vivado

 

[ads-ee]

output [10 : 0] wr_data_count;

// synthesis translate_off

  FIFO_GENERATOR_V9_3 #(

the results so far don't show anything wrong.

I think coshy doesn't understand that Xilinx primitives won't show up as having lower levels of heirarchy as in the first post.
Now with this latest post the FIFO_GENERATOR_V9_3 is an instance in another file, but synthesis is disabled before it even reaches the primitive core so it won't show up in Synplify's hierarchy as it's never seen by the tool.

I'm still not sure what the point of this thread is.