rakeshk.r
Member level 2
I have written a gate level code for adder in verilog. The output the adder is shown below. As you can see the sum and cout are always in z. I don't know why. Could you check what am i missing ? Thanks for your time.
Code:
module tb();
reg a, b, cin;
wire cout, summ;
FA_gatelevel gatelevel(.a(a), .b(b), .cin(cin), .summ(summ), .cout(cout));
initial begin
#10 a = 0; b = 0; cin = 0;
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
initial begin
$monitor("a = %0h, b = %0h, cin = %0h, summ = %0h, cout = %0h at time = %0t",a,b,cin,summ,cout,$time); // gate level
#200 $finish;
end
endmodule
Code:
module FA_gatelevel(a, b, cin, summ, cout);
input a,b,cin;
output summ,cout;
FA_co ins_co(.a(a), .b(b), .cin(cin), .cout(cout));
FA_sum ins_sum(.a(a), .b(b), .cin(cin), .summ(summ));
endmodule
Code:
module FA_co (a, b, cin, cout);
input a, b, cin;
output cout;
wire ab, bc, ca;
and g0 (a,b,ab);
and g1 (b,c,bc);
and g2 (c,a,ca);
or g3 (ab,bc,ca,cout);
// equation: cout = (a.b) + (b.c) + (c.a)
endmodule
Code:
module FA_sum(a, b, cin, summ);
input a, b, cin;
output summ;
xor g0 (a,b,cin,summ);
endmodule
