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Compile ultra problem in dc shell

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cyrax747

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Hi

I am running a hierarchical design in dc shell. I loaded design and libs sdc. Now when i do link it is saying 9 unsolved references.What should i do to fix this??

When i do Compile _ultra it exits shell with command code 0; only compile command is working fine. Please clarify.
 

it means you probably forgot to include some of the verilog files.
 

hi,

what could be other reason,because i have used all verilog files,earlier it is 29 now 78 files i read in to design thats y i am asking.
 

cyrax747 said:
Hi
I am running a hierarchical design in dc shell. I loaded design and libs sdc. Now when i do link it is saying 9 unsolved references.What should i do to fix this??
When i do Compile _ultra it exits shell with command code 0; only compile command is working fine. Please clarify.
Click to expand...

Your top design can not be link correctly.
This could be lack of design files, or verilog syntax error in some file cause that sub-designs can not be loaded.
Please check log files again.

Without successful link, compile command will not work.
 

There is no compilation errors. Presto compilation is fine. So now what could be the problem?
 

cyrax747 said:
There is no compilation errors. Presto compilation is fine. So now what could be the problem?
Click to expand...

Post the log file.

- - - Updated - - -

And try to analyze verilog files, then elaborate top design instead.
 

Hi,

Please make sure that you have loaded all the dbs that are required in the design for the Memories,Pads etc ...

compile_ultra fails if the design is not linked correctly.

Make sure the Link report is clean and returns 1, Without any warnings.

Regards
 

no memories no apds,just rtl only.i read all and i have tried still there are errors.

what i have observed is 8 unsolved references.

there are 2 rtl files not read,later i read in to the memory.Now if i do they are linking.But if i change the current esign to top,again same 8 unresolved references.

help me know.
 

badly late response, but could you post your script to run dc ?
 

read_rtl

read_libs

link

elaborate <top name>

compile_ultra

this is sequence of commands i follow.
 

Is there any hard-core like standard cell instanced inside your rtl module ?
I wonder if they can be read before the library was read in !
 
The problem you are having doesn't show up as a hard Error. Search for "Cannot find" or "LBR-1" within the log file.

These searches should provide the design name that the linker is expecting but cannot find. It's either an RTL file that you are missing, a macro or .db.

Here is an example from one of my designs, I renamed the design name:

Warning: Cannot find the design 'ABC_DESIGN_NAME' in the library 'WORK'. (LBR-1)

Let us know if this works for you.
 
Last edited:

TonyLS said:
The problem you are having doesn't show up as a hard Error. Search for "Cannot find" or "LBR-1" within the log file.

These searches should provide the design name that the linker is expecting but cannot find. It's either an RTL file that you are missing, a macro or .db.

Here is an example from one of my designs, I renamed the design name:

Warning: Cannot find the design 'ABC_DESIGN_NAME' in the library 'WORK'. (LBR-1)

Let us know if this works for you.
Click to expand...

Yes, that is why I asked the OP to post the logfile.
 
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