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[SOLVED] Converted tricell instance critical warning

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flote21

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Hello guys!

I am wondering what does this critical warning means?

The scenario was:

I have been working with VIVADO 2015.4. Then I installed the last version of VIVADO 2016.3 and when i import this project I got these warnings which I did not have them with the 2015.4 vivado version.

I am working with the eval board of xilinx ZC702. And my block diagram consists in the zynq processors + several custom ips...

Anyone knows the origin of this warning? Is it critical to normal working of the system or Should I ignore them?

Thanks in advance.

kk.jpg
 

are you using tri-state logic inside the FPGA to multiplex something, that is what I think it is fixing. There are no internal tri-states inside a Xilinx FPGA.

Can't be sure this is the problem as you've provided inadequate information (this is also probably why I'm the only person to answer this after 3 days and 146 views)
 
Hi!

I am not using any tri-state logic inside of the FPGA. In fact this design was working properly without any critical warning in the 2015.4 version of VIVADO.

Thanks anyway for your help.

ads-ee said:
are you using tri-state logic inside the FPGA to multiplex something, that is what I think it is fixing. There are no internal tri-states inside a Xilinx FPGA.

Can't be sure this is the problem as you've provided inadequate information (this is also probably why I'm the only person to answer this after 3 days and 146 views)
Click to expand...
 

Then I installed the last version of VIVADO 2016.3 and when i import this project I got these warnings which I did not have them with the 2015.4 vivado version.
Click to expand...
I don't know if it'll solve the problem, did you try to ''regenerate output products" and then re-compile and re-synth your design?
btw- Critical Warnings shouldn't be ignored.

I am almost sure this problem is entirely due to porting from 2015.4 to 2016.3.

Can understand your situation. Me too switched to Viv 2016.3 from 2015.4 this week and faced a some signal value display problem in the waveform viewer. My thread is still not solved under the sub-forum, Simulation and Verification --> Signal value not completely displayed in waveform window. Someone says that my problem is reported to the factory, don't know hen this'll be resolved.
 

Hi!!!

Yes i tried to regenerate output products and everything and the problem is still there...I asked to xlinx in their forums and nobody is able to give me a hand :-(

Thanks anyway.

dpaul said:
I don't know if it'll solve the problem, did you try to ''regenerate output products" and then re-compile and re-synth your design?
btw- Critical Warnings shouldn't be ignored.

I am almost sure this problem is entirely due to porting from 2015.4 to 2016.3.

Can understand your situation. Me too switched to Viv 2016.3 from 2015.4 this week and faced a some signal value display problem in the waveform viewer. My thread is still not solved under the sub-forum, Simulation and Verification --> Signal value not completely displayed in waveform window. Someone says that my problem is reported to the factory, don't know hen this'll be resolved.
Click to expand...
 

are any of the IP cores not at the correct version for the tools, signified by a locked symbol on the core in the IP Sources tab of the Sources window? Regenerating the core without upgrading it might very well result in problems with the core not being correctly implemented.
 

Hello guys!!

Finally I reached the solution. The problem was the IP core itself. Some of the signals were tied to high impedance : 'Z' and this was the reason of the critical warning. After correct this issue, critical warnings were gone.

Thanks everybody for the support!!

ads-ee said:
are any of the IP cores not at the correct version for the tools, signified by a locked symbol on the core in the IP Sources tab of the Sources window? Regenerating the core without upgrading it might very well result in problems with the core not being correctly implemented.
Click to expand...
 

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