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System Verilog : understanding logic datatype

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Ashish Agrawal

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Hi All,

I need some help in understanding the "logic" in system verilog.
I am familiar to code RTL in verilog but now requirement is for system verilog.
I am confused between "logic" and "wire".

1. In verilog all the input ports must be of "wire" types, which is implicit if you don't define any types. Is this requirement same for system verilog? or input can be of "logic" types as well? what will be the advantage of defining input as "logic"? What will be the default type if nothing is defined? can an input be defined for both the types "wire" and "logic"?

2. What is the difference in following statements
wire a;
logic a;
wire logic a;
logic wire a;

Thanks in advance.
-Ashish
 

Read this

The following cases
Code: 
wire logic a;
logic wire a;
are both syntax errors.

IMO SV should have never created new types for the same thing, really stupid decision. Based on bad teaching practices and badly written books describing the types.

wire: continuous assignments and interconnection between instantiated modules.
reg: procedural assignments, i.e. assignments in tasks, always blocks, etc.
logic: continuous or procedural, based on context whether or not it implements combinational or sequential logic.
 

ads-ee said:
Read this
Click to expand...
Thanks for this link. But I am still confused when it comes to input ports. I have seen the RTL in system verilog which has inputs defined like below

Input a,
Input wire logic b,
Input logic c,
Input wire d,

I am unable to understand the difference in the above definitions.

It will be helpful if someone can answer the point 1 in my first post.

-Ashish
 

SystemVerilog made two major enhancements in this area.

First, it separated the concept of a data type, which defines the way expressions get evaluated, from the a signal kind, which defines how assignments to a signal work.

Verilog always had the concept of Nets and Variables, but no keywords with those names. People just referred to Wires and Reg's. Nets are signals that are driven by one or more continuous processes, and there is a built-in resolution function that deal with the case when there are different values being driving simultaneously. Variables hold a value from a procedural assignment and that value holds until another there is another procedural assignment. There is no possibility of simultaneous procedural assignments to a signal - that is a race and the last assignment wins.

SystemVerilog added the concept of user defined types to enable concepts like structures, enumerations, and other typedefs. People wanted to be able to have user defined types with nets as well as variables. So what they did was allow an optional datatype after the wire keyword. So you can now do
Code: 
typedef struct {logic [2:0] field1;
                      logic [4:0] field2; } my_type;

wire my_type w;
Now you can refer to w.field1 and w.field2 in your code. When you don't specify a datatype after the wire keyword, there is an implicit logic datatype. This makes SystemVerilog backward compatible with existing Verilog code.
Code: 
wire a; //is implicitly equivalent to 
wire logic a;
SystemVerilog also created a var keyword to explicitly declare a variable, mainly to deal with a problem in port declarations. The default signal kind for a port is a wire, so if you have the var keyword is used to change that default.
Code: 
module mod(output a, var logic b, logic c);  //is implicitly equivalent to 
module mod(output wire logic a, output var logic b, output var logic c);  // explicit

The other change SystemVerilog made was to allow a single continuous assignment to a variable when there are no other assignments to that variable. Since there are very few signals in a design, you can make everything a variable and only use wires when there are multiple drivers.
 

dave_59 said:
Code: 
module mod(output a, var logic b, logic c);  //is implicitly equivalent to 
module mod(output wire logic a, output var logic b, output var logic c);  // explicit
Click to expand...
How come output a can be equivalent to output wire logic a ? As you mentioned that for ports "wire" is implicit declaration. But how can it take "logic" implicitly until we define it explicitly.

Could you also tell me, what would be the advantage of declaring input as "logic"? (Any how an input can't be driven inside the module, so there is no point of assigning a value to an input in continuous/procedural statement)

-Ashish
 

Because I said the default data type for a wire signal is logic. If you have an internal (non-port) declaration:

Code: 
wire a; // is implicitly the same as 
wire logic a; // explicit

logic wire a; // is illegal.

There's no advantage in using this explicit form, except that it is more consistent to a SystemVerilog user that has never used Verilog. It also makes more sense when introducing parameterized types. You should be able to use logic as well as any user defined type for the data type of a wire.

Code: 
module m #(type T)(input wire clock, T in, output var T out);
always @(posedge clk)
                     out <= in;
endmodule


module top;

m #(my_type) m1(...);
m #(logic) m2(...);
 
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