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    imbichie's Avatar
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    Cochin/ Kerala/ India or Bangalore/ Karnataka/ India
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    Inferring DSP blocks in Synplify Premier using SDC Constraints

    Hi All,

    I am using Virtex 7 1157 FPGA.
    My design with RTL is freezes. I cannot modify a single line in the RTL.
    I needs to infer the DSP blocks for particular adder logic in my design.
    During the Synplify synthesis, I observed that automatically these adder are not using DSP blocks.
    Is there any *.sdc constraints for inferring the DSP block for adders (also for XOR) logic in the design.
    IN RTL i know by using the syn_multsyle will do this.
    But RTL is freezes, so only option is the SDC file.
    In vivado tool we have options for this :
    set_property use_dsp48 yes [get_cells <signal>]
    I need the similar sdc constraints for synplify.

    After the synplify I will be using vivado for place and route.
    Last edited by imbichie; 19th August 2016 at 02:59.
    Thanks & Regards,
    Shibin Bose Kavara

    " Take chances, make mistakes. That's how you grow. Pain nourishes your courage. You have to fail in order to practice being brave "

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