Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Replicated logic optimization

Status
Not open for further replies.
R

rac70

Newbie level 6
Joined
Jan 7, 2015
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
114
Hi all,
My RTL code contains exact 6 replications of same logic as it includes 6 different buffers.
So, the code complexity was getting increased. I tried, using common function for the logic, but even the device utilization was the same. Can there be a better way to design? Waiting for your reply.
Thankyou.
 

If something is replicated 6 times, it will use 6x the logic. Unless you design it some way to reuse some logic. But you didn't post your design or the problem, so there is little we can do.
 

There were many blocks pointing the same scenario here. As you said the logic utilization will be 6-times, can there be a solution for reducing the complexity of code , due to the replications the code size also got increased.
 

I'm not quite sure what "replication" means for you.

- using the same logic function for different signals
- duplicating logic (creating redundancy) to simplify routing or improve timing

In the former case, no optimization can take place.
 

rac70 said:
There were many blocks pointing the same scenario here. As you said the logic utilization will be 6-times, can there be a solution for reducing the complexity of code , due to the replications the code size also got increased.
Click to expand...

Without the application or the code, we can only speculate as to what you can do.
If you want more help - post either the code or the problem.
 

As FVM said,
It is same logic , but different signals are used. The functionality was same, but each always block constitute the same functionality w.r.to their data presence at valid signal. The problem is the duplication of same logic for 6 times. will there be any chance of optimizations of this kind. I tried using functions, but it does not make any sense to me.
 

This is hardware design.

I have no idea what you are doing, but I'll propose this: An inner product is done by multiplying N elements then adding them.

Each multiply and each add is the same. Performing the operation can be done with N multiply-add units. It can be done at half that rate with half as many. At 1/10th rate with 1/10th units. It can even go lower if the multiply-add unit is designed to take multiple cycles.
 

It is same logic , but different signals are used. The functionality was same, but each always block constitute the same functionality w.r.to their data presence at valid signal. The problem is the duplication of same logic for 6 times. will there be any chance of optimizations of this kind. I tried using functions, but it does not make any sense to me.
Click to expand...
You are just experiencing how hardware logic synthesis works. Using a HDL function or procedure means creating parallel logic instances.

vGoodtimes mentioned the option to serialize logic usage at the expense of speed. To do so, you need to design a sequential state machine, multiplexer and possibly extra registers for the involved signals. Can be useful for some applications, but it's not the main stream of FPGA design.
 

rac70 said:
Hi all,
My RTL code contains exact 6 replications of same logic as it includes 6 different buffers.
So, the code complexity was getting increased. I tried, using common function for the logic, but even the device utilization was the same. Can there be a better way to design? Waiting for your reply.
Thankyou.
Click to expand...

My understanding is that, you have 1 RTL module. It has 1 input and some outputs. ( for example )
Your design has 6 signals and you need to do the function with all of those inputs.
Then, you instance the module 6 times in your design, right ?
If so, there is no way to reduce in case your design need to work with those inputs in parallel.

If only 1 input works at 1 point of time, it is ok to use 1 instance and switch the input to have smaller code.
 

slutarius said:
My understanding is that, you have 1 RTL module. It has 1 input and some outputs. ( for example )
Your design has 6 signals and you need to do the function with all of those inputs.
Then, you instance the module 6 times in your design, right ?
If so, there is no way to reduce in case your design need to work with those inputs in parallel.

If only 1 input works at 1 point of time, it is ok to use 1 instance and switch the input to have smaller code.
Click to expand...

This may be the case - or it may not be the case - it depends on your design.
Lets assume you have 4 inputs.
Each input is only valid for 1 in every 4 clocks.
Then you may be able to use one instance of your logic that is running on every clock.
The bandwidth is the same, but the logic utilisation is different.

It is really design dependent and cannot be formalised in black and white rules.
 

TrickyDicky said:
This may be the case - or it may not be the case - it depends on your design.
Lets assume you have 4 inputs.
Each input is only valid for 1 in every 4 clocks.
Then you may be able to use one instance of your logic that is running on every clock.
The bandwidth is the same, but the logic utilisation is different.

It is really design dependent and cannot be formalised in black and white rules.
Click to expand...

Yes, I agreed that it is case by case.
Just want to understand the OP problem in details.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top