Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

data memory access cycles in arm cortex a9

Status
Not open for further replies.
S

Sunayana Chakradhar

Member level 5
Joined
Oct 24, 2014
Messages
85
Helped
2
Reputation
4
Reaction score
2
Trophy points
8
Activity points
742
Hello All,

I am searching for data memory access cycles in arm cortex a9 which should include arbitration overhead by specific bus (AXI or LMB etc). I searched it in the arm cortex and microblaze manual. Please tell me where i can find it.
 

For
data memory access cycles in arm cortex a9
Click to expand...
perhaps the ARM Cortex A9 micro-architecture specification! Not sure...
 

If you're asking about access to external memory - it also depends on the memory controller. I.E: ARM won't have all the answers.
 
As this is a Zynq any peripheral that is not included as part of the PS is going to be in the PL, which being configurable with an HDL means that the latency of the entire path isn't set in stone.

Arbitration overhead will have to account for the number of things being serviced, which can vary and the arbiter itself add varying amounts of latency depending on the implementation. To determine the latency to a memory on the AXI would require analysis of a worst and best case scenario of the access knowing the arbitration latency and the PS latency for the access.
 
I basically want to know the access cycles of DDR, block RAM and on chip memory over the AXI

- - - Updated - - -

where do i find the PS access latencies?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top