QMA
Member level 4
Dear all
how can I instantiate a module for example 'abc' in verilog. it has inputs for example 'a' and 'b' with output 'c'. let I instantiate this abc module in 'jkl' with inputs 'j' and 'k'. the input 'j' is equal to output 'c'. How can I do this?
1. shall i declare 'j' as input?
2. if not necessary then i think 'j' will be a reg. Am I right?
what will be programming statement
how can I instantiate a module for example 'abc' in verilog. it has inputs for example 'a' and 'b' with output 'c'. let I instantiate this abc module in 'jkl' with inputs 'j' and 'k'. the input 'j' is equal to output 'c'. How can I do this?
1. shall i declare 'j' as input?
2. if not necessary then i think 'j' will be a reg. Am I right?
what will be programming statement