pradeep007
Newbie level 3
spi(serial peripheral interface) modelling and verification
please help me to write testbench for the spi(serial peripheral interface) verilog code.please go through the attachments for the problem statement and the verilog code .
please help me to write testbench for the spi(serial peripheral interface) verilog code.please go through the attachments for the problem statement and the verilog code .
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 module spi(clk, csz, MISO,MOSI); input clk, csz, MOSI ; output MISO ; wire MOSI; reg MISO ; reg [6:0] address; reg [7:0] memory [0:127]; reg [7:0] data; reg rw; reg [3:0] i=0; reg [2:0] j=0,k=0,l=0; integer m,n; initial begin for (m=0;m<128;m=m+1) begin memory[m]=8'b0;\\initialise memory to zero end end always@(posedge (clk))begin if(csz==0)begin if(i<=7)begin address[k] <= MOSI; k=k+1; end if(i==7)begin rw <= MOSI; end if (i>=8)begin if ((rw==1))begin memory[address][j] <= MOSI; data[j] <= MOSI; j=j+1; end else begin MISO <= memory[address][l]; data[l] <= memory[address][l] ; l=l+1; end end assign i=i+1;\\counter which keeps track of clock for read and write operation end else begin data <= 8'b0 ; address <= 8'b0 ; i<=4'b0 ; j<=3'b0 ; k<=3'b0 ; l<=3'b0 ; rw<=1'bx; end end endmodule