MH.AI.eAgLe
Newbie level 4
[moved]full verilog code for transmitter module , channel module and reciever module
HI
i tried to write this code but i was not successful , first i tried to write a top module consists of 3 modules (transmitter,channel,reciever) , my 7-bit data would passed from a channel , i consider 3-bit for parity check and i assumed only the 7-bit data would be changed (because of channel affect ), i applied it by this way : $random | [9:3]data_chk
[9:0]data_chk // i merged data with 3-bit parity check : [9:3]data and [2:0]chk
Since I could not do anything so I need your help
thanks
HI
i tried to write this code but i was not successful , first i tried to write a top module consists of 3 modules (transmitter,channel,reciever) , my 7-bit data would passed from a channel , i consider 3-bit for parity check and i assumed only the 7-bit data would be changed (because of channel affect ), i applied it by this way : $random | [9:3]data_chk
[9:0]data_chk // i merged data with 3-bit parity check : [9:3]data and [2:0]chk
Since I could not do anything so I need your help
thanks