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unconstrained array in verilog

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harian

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i have came to know that verilog doesnot support uncontrined array type. i need memory to store inputs before writing to txt file. the number of inputs are unknown. it is obviously not for synthesis purposes.is there way to do declare an array of unknown size .. i am thinking about this
Code: 
integer length;
reg [5:0] mem [length:0];
.....
@(initial_step)
lenth = 0;

@(signal)
mem[0]= var1;
length = lenght +1;
 

Hi,

I don't know if verilog supports that. I think not (don't know if system verilog is better in this way)...but...
What would I do in this case is to create simulation script which is doing following:

1: to go through input file and calculate nr. of inputs
2: to create verilog include file with declaration of your array
3: to start simulation

Maybe quite complicated, but should be functional
 

Hi,

I don't think it is possible to change the array size during runtime.

the number of inputs are unknown
Click to expand...
The number of inputs must be known.
But the number of samples (data sets) may be unknown. I recommend you should limit it to a fixed count.
"Unlimited" isn't possibke either.

Klaus
 

SystemVerilog supports dynamic arrays or queues that can be sized at run time. ModeslSim and most other simulators support this just by using a *.sv file extension.

Code: 
reg [5:0] mem[]; // dynamic array

initial begin
     mem = new[length];
or
Code: 
reg [5:0] mem[$]; // queue

initial begin
     mem.push_pack(var1); // adds one element to the queue.
 

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