hossein_jalali
Newbie level 4
Hi guys;
I've recently simulated a SAR ADC in Cadence & now I want to measure the INL & DNL of the ADC. Each conversion takes 3us. I have designed this ADC for 5 bits & therefore we are going to have 32 states in the output. I've attached my 5 bit output to a 5 bit ideal DAC so that I can compare the analog input slow ramp to the digital codes which are then converted to analog by this ideal DAC.
What do you think the simulation time should be?? I have tried 1920us so that I can collect 20 samples for each code. Every code takes 3 us & therefore 32*20*3us=1920us.
How can I plot the INL & DNL after the simulation is done?? We are going to have analog input ramp versus time & also output data (converted to analog) versus time. How should we calculate & plot INL & DNL by having these two??
Thanks.
I've recently simulated a SAR ADC in Cadence & now I want to measure the INL & DNL of the ADC. Each conversion takes 3us. I have designed this ADC for 5 bits & therefore we are going to have 32 states in the output. I've attached my 5 bit output to a 5 bit ideal DAC so that I can compare the analog input slow ramp to the digital codes which are then converted to analog by this ideal DAC.
What do you think the simulation time should be?? I have tried 1920us so that I can collect 20 samples for each code. Every code takes 3 us & therefore 32*20*3us=1920us.
How can I plot the INL & DNL after the simulation is done?? We are going to have analog input ramp versus time & also output data (converted to analog) versus time. How should we calculate & plot INL & DNL by having these two??
Thanks.