haianh
Newbie level 6
Hi, I have the logic that generate DDR output signal e.g.
assign DDR_out = clk ? DDR_pos_reg : DDR_neg_reg
and using DC to synthesis it. clk signal is the select of the mux and create data value on both edge. This architecture is valid as mentioned in https://www.edaboard.com/threads/257864/ thread.
But I checked the clock tree log file and see it report DDR_out is in clock path. I think it is not correct and need to add some DC constraints to help tool understand my intention. What constraints can I use in my case? Thanks
assign DDR_out = clk ? DDR_pos_reg : DDR_neg_reg
and using DC to synthesis it. clk signal is the select of the mux and create data value on both edge. This architecture is valid as mentioned in https://www.edaboard.com/threads/257864/ thread.
But I checked the clock tree log file and see it report DDR_out is in clock path. I think it is not correct and need to add some DC constraints to help tool understand my intention. What constraints can I use in my case? Thanks