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  1. #1
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    Microwind2 - Post Layout Simulation in HSPICE

    Hi,

    I designed a layout of an Inverter in Microwind2 using 0.12um foundry [CMOS 0.12um - 6 Metal (1.20V, 3.30V)].

    I wanted to do a post layout simulation in HSPICE_Z-2007.03. So from Microwind I got the SPICE Netlist and saved it as *.sp file for HSPICE input. I also added the line ".OPTIONS LIST NODE POST" in the netlist. Then I simulated the *.sp file in HSPICE and observed the graphs from Avanwaves. The input and output curve doesn't match with the curve of an inverter. {The Output is greater than the input. I attached the curve here}

    I can't figure out the problem. What is wrong with it?

    # The layout is correct. Microwind2 simulation shows curves of perfect Inverter.

    # From Microwind2 I generated the Netlist for both MOS Models Empirical Level 3 and Advanced BSIM4, none of them works.

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  2. #2
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    Re: Microwind2 - Post Layout Simulation in HSPICE

    Your graph doesn't say which trace is which, but I'd assume
    the square blue trace is input since it's ideal looking. Then the
    other, presumably output, says to me that you've got no ground
    connection and no load, and are just shuttling input charge back
    and forth to the output through some device that's attached
    to +1.2V and leaking enough to set the DC solution there.

    It would be much better if you bothered to include the circuit
    you are asking about.



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  3. #3
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    Re: Microwind2 - Post Layout Simulation in HSPICE

    There is Ground Connection in the layout and Vdd+ = 1.2 Volt.

    I attached the layout diagram.


    Here is the SPICE Netlist I got from Mucrowind2:


    And you are right about the curve. The blue line is the input. The input clock is also 1.2 Volt. (Same as Vdd+)


    Code:
    CIRCUIT E:\VLSI Design\Inverter_4Lambda.MSK
    *
    * IC Technology: CMOS 0.12µm - 6 Metal
    *
    VDD 1 0 DC 1.20
    VINPUT 6 0 PULSE(0.00 1.20 0.23N 0.02N 0.02N 0.23N 0.50N)
    *
    * List of nodes
    * "OUTPUT" corresponds to n°3
    * "INPUT" corresponds to n°6
    *
    * MOS devices
    MN1 0 6 3 0 N1  W= 0.24U L= 0.12U
    MP1 1 6 3 1 P1  W= 0.24U L= 0.12U
    *
    C2 1 0  0.346fF
    C3 3 0  0.218fF
    C4 1 0  0.133fF
    C6 6 0  0.081fF
    *
    *
    * n-MOS BSIM4 :
    * low leakage
    .MODEL N1 NMOS LEVEL=14 VTO=0.40 U0=0.050 TOX= 3.5E-9 LINT=0.010U 
    +K1 =0.450 K2=0.100 DVT0=2.300
    +DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
    +NFACTOR=  1.6 U0=0.050 UA=3.000e-15
    +WINT=0.020U LPE0=23.000e-9 
    +KT1=-0.060 UTE=-1.800 VOFF=0.050
    +XJ=0.150U NDEP=170.000e15 PCLM=1.100
    +CGSO=100.0p CGDO=100.0p
    +CGBO= 60.0p CJSW=240.0p
    *
    * p-MOS BSIM4:
    * low leakage
    .MODEL P1 PMOS LEVEL=14 VTO=-0.45 U0=0.018 TOX= 3.5E-9 LINT=0.010U 
    +K1 =0.450 K2=0.100 DVT0=2.300
    +DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
    +NFACTOR=  1.6 U0=0.018 UA=3.000e-15
    +WINT=0.020U LPE0=23.000e-9 
    +KT1=-0.060 UTE=-1.800 VOFF=0.050
    +XJ=0.150U NDEP=170.000e15 PCLM=0.700
    +CGSO=100.0p CGDO=100.0p
    +CGBO= 60.0p CJSW=240.0p
    *
    * Transient analysis
    *
    .TEMP 27.0
    .TRAN 0.30PS 2.00N
    .PROBE
    .END
    Last edited by bigdogguru; 20th May 2015 at 13:40. Reason: Added CODE or SYNTAX Tags



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