shaiko
Advanced Member level 5
Hello,
I'm using this micowire EEPROM:
https://ww1.microchip.com/downloads/en/DeviceDoc/21797L.pdf
and having trouble understanding on what edge of SCLK the master shall propagate data to the EEPROM and on what edge it should sample the incoming data from the EEPROM...
FIGURE 2-5 (page 8) suggests that data is propagated on the falling edge of SCLK and sampled on the rising edge (like with SPI mode 0). Smart and simple...
However,
the first paragraph of section 3.2 (page 11) says something different:
How can it be done reliably without compromising setup times??
What am I missing here?
I'm using this micowire EEPROM:
https://ww1.microchip.com/downloads/en/DeviceDoc/21797L.pdf
and having trouble understanding on what edge of SCLK the master shall propagate data to the EEPROM and on what edge it should sample the incoming data from the EEPROM...
FIGURE 2-5 (page 8) suggests that data is propagated on the falling edge of SCLK and sampled on the rising edge (like with SPI mode 0). Smart and simple...
However,
the first paragraph of section 3.2 (page 11) says something different:
This means that the master samples data from the EEPROM on the rising edge while the EEPROM propagates data on that same edge?!Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
How can it be done reliably without compromising setup times??
What am I missing here?