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Microwire sampling and propagation timings

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shaiko

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Hello,
I'm using this micowire EEPROM:
https://ww1.microchip.com/downloads/en/DeviceDoc/21797L.pdf
and having trouble understanding on what edge of SCLK the master shall propagate data to the EEPROM and on what edge it should sample the incoming data from the EEPROM...

FIGURE 2-5 (page 8) suggests that data is propagated on the falling edge of SCLK and sampled on the rising edge (like with SPI mode 0). Smart and simple...

However,
the first paragraph of section 3.2 (page 11) says something different:
Opcodes, address and data bits are clocked in
on the positive edge of CLK
. Data bits are also clocked
out on the positive edge
of CLK.
This means that the master samples data from the EEPROM on the rising edge while the EEPROM propagates data on that same edge?!
How can it be done reliably without compromising setup times??
What am I missing here?
 

You're misinterpreting the statement.

address/data bits clocked in on positive edge....i.e. they were clocked out (master device) on the falling edge and sampled (microchip) on the rising edge

data bits are clocked out on the positive edge...i.e. the bits are clocked out (microchip) on the rising edge and sampled (master device) on the falling edge

btw. this is not a SPI interface, so I don't expect it to be compatible with mode 0, which it doesn't look like it is, but the description is consistent with the drawing.
 
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