Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to ctrl the operation of register

Status
Not open for further replies.
A

anusha vasanta

Member level 1
Joined
Sep 23, 2014
Messages
34
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
251
HI everyone,
i had a doubt help me, i had a tmp_reg of 128 bits in starting time that tmp_reg should contain a mic value of 128 bits , and from next onwards it should contain some other result, just like this it should run sequentially
eg:
tmp_reg= mic;
gen block
for(m=0;m<5;m=m+1)
assign b_0[m]=tmp_reg^d[(m*128)+127:(m*128)]
TOP(b_0[m],b_r[m])//instantiation
assign tmp_reg=b_r[m]

here everything i want is my block should run sequentially as per architecture point and my register for first m=0 it should contain tmp_reg with mic value and from next m=1 onwards tmp_reg should contain the instantiation result.
i was just troubling for implementing this.
just suggest me any help
thanku all
 

Before you write this code, I would suggest you to first pick up a good HDL book and read it.
The above piece of code is not sequential, and uses a combination of generate and for loops. U need to understand how HDL is interpreted as hardware, the syntax of several constructs (like generate & for loops) and when to use where.
 

can u suggest any good books which even had verilog-2001 constructs
 

I don't know about Verilog 2001. But I read verilog from Bhaskar. U can pick up any Verilog book I suppose maybe not focusing on V-2001.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top