RTL Always block for FSM

RTL Always block styles

I've seen RTL implementations where

1. Only sequential always block is used, always@(posedge clk), with assign statements for combinational logic
2. Comb and sequential always block is used, always@(*) and always@(posedge clk) to separate the comb and seq logic

I have two questions:
a) Seeing that the same logic can be coded in two different ways, why is 2. more preferred than the other? Seems like 1. option is easier to code and read.
b) Why does FSM using 1) style work? (I thought we aren't supposed to use combinational and sequential logic in the same always block.)

Thanks!

Re: RTL Always block styles

Hi,

Before we start coding any design, we need to know what is combinational and sequential logic.
By using blocking and non-blocking we can create different logic. Once the concept of BA and NBA is understood, i think you can clear your doubts yourself.

Please try to google about BA and NBA. If you still not able to understand, let me know.

Thanks,
Vivek.s

Re: RTL Always block styles

I do understand BA and NBA but I am still unsure about those questions.

If you could answer my questions, it would greatly help to clear my confusion.. Thanks

A good point to start, I think:

b) Why does FSM using 1) style work? (I thought we aren't supposed to use combinational and sequential logic in the same always block.)

Click to expand...

From a hardware viewpoint, synchronous logic (=clock sensitive or sequential logic) uses a combination of combinational logic gates and registers, except for trivial cases. If you are describing registered logic in an @(posedge clk) block, there will be also sequential logic in front of the registers.

In case of a state machine, you have registers holding the present state vector and combinational logic feeding nextstate for each state vector bit. This principle structure exists in any synchronous state machine, independent of the description style. In the "two always block" style, you describe the combinational logic separately, in a "one always block" design, it's implicitely embedded in the clock synchronous always block. Or part of it described as continuous assignment. You can use both styles in a way that there's no functional difference at all.

Behaviour of state machine outputs is a bit different. In the two block design, outputs are combinational, in the single block registered without additional provisions. This may be more wanted or unwanted, depending on the design purpose.

As a final remark, I agree with the view that the single always block (or single VHDL process) "option is easier to code and read". But this is a purely subjective point.

For complex RTL designs with multiple conditions, use of assign statements can be very hard to work with ( for example you have to use multiple "?" conditional operator making the code hard to read. So you can always always@(*) to design the combinational part of the circuit where you can use multiple behavioral statements(case and if) to design.
I did not get the second question. As always@(posedge clk) is solely used for designing the sequential part of the logic while assign statements are used for combinational logic used out of the always block. So you are not using same always block for designing your sequential and combinational logic.