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How to design a high performance mos switch?

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yyliang

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Hello, I am designing a switched capacitor integrator,but I encountered a difficulty in design the switches, it seems that there is current leakage from the source or drain,can someone help me?How can I get a high performance mos switch?
Thanks in advance.
 

Is there any reason why you can not use integrated switch CD4066?
Inside you will find 4 bilateral switches.
 

it is diffcult to do.
contact the foundry, require them well control.

And you can add the switch "L", make sure not the smallest .
 

first the ratio of W/L should be optimized, then choose a suitalbe absolute value of W and L. If still couldn't satisfy requirement, use dummy device or adopt bootstraping or bottom-plate sampling technique.
 

mos switch for Sample/hold need low leakage , simple mos like CD4016
is better than CD4066 ,

but cmos switch CD4066 have low Rds ..

In asic design , you cn use "dummy sw" reduce charge_inject & clock feed_thru
maybe "unless" --> some porfessor said even text book said
add dummy switch can reduce charge_inject

another problem is mos Rds & Vth drop on mos switch
in some volt double circuit like charge pump use pmos for Hi-v input
(nmos vo= vin -vtn) but even though .. vin = 2* vin -v1 ..

I simulation find Vo= 6.16v not 3.3v*2=6.6 still have volt drop
cmos switch I use 20/0.5 * 200 size ..

have anyone ever design charge_pump ASIC , Io=100ma
can you tell me how to design mos switch
 

The use of differential circuits will help decreasing charge injection. Look at basic lieterature like that CMOS DESIGN (Razzavi).
 

Should the clock of PMOS and NMOS be definitely opposite phase?
 

I "guess" eda4foru means , some use switch circuit like
flash A/D convert use switch cap + preamp cirucit usually use
differential signal path ..

but I problem is use mos switch for , charge_pump circuit ..
pump 1.5v -> 5.5v output , and use good switch reduce volt_drop & Rds on ..
 

u can use a dummy switch or a transmission gate switch to minimize the leakage from source and drain.also for the switch u require the on resistance to be very low so optimize the w/l ratio.clock for dummy switch is somewhat delayed w.r.t. switch
 

increase the L and optimize the W
 

For the analog ic design, you just need to select right topology, then base on the what's clock frequency and signal frequency is, work out a reasonable settling time, to decide the switch W and L, then use a bootstrapping clock for critical switch. Please forget dummy switch, it is not true at some case.
 

can you give some information about efficiency of clock bootstrapping for (pass-gate) switch and bulk-source forward-biased polarization at 0.12u technology?
 

Leackage is always there. The problem is how much.
 

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