Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Clock skew is the maximam difference of the delay time from the clock source to all the clock port of the flip-flops in that clock domain. And Clock delay, in this sense, is the average(mean) of the above delays.
PLL is for phase lock loop. In the sense of clock synthesizer, it contains a VCO(valtage control Oscilliator), generating output clock with a frequency M/N of the input reference clock, and the feedback loop that ensures the M/N relationship and the stability.
DLL is for Delay lock loop, instead of VCO, it contains only Delay array, that can only adjust the delay(phase), from the input reference clock, and sometimes, capable of generating 2X clock(Xilinx DCM).
1- Clock Skew: always measure the delay between two nodes drived from the same clock source and ideally the clock edge should arrive at the same time on both.
2- Clock delay: mainly defined for a transmission line ( or trace) so it may defined as x ns/ y mm. it also can be define the delay between two nodes (clock skew) by knowing the c/c's of the track connecting these nodes.
3- PLL: the conventiona analog Phase Locked Loop.
4-DLL: Delay or Digital locked Loop the digital implementation of PLL.
the skew generally mean clock path delay difference of two dff that are close.
but for clock tree the skew means maximus delay difference of clock path between all dff's that the clock drives.
clock delay means latency that delay from clock source to dff's CK pin.
PLL is phase-lock-loop, it is generally a analog.
DPLL is all-digital pll
DLL is delay-lock-loop. it also can be analog or all-digital.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.