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  1. #1
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    how can we reduce IOB in FPGA

    dear all
    can some one tell me what's the use of IOB in FPGA, In my project after synthesis (ISE), in the design summery, it is showed that 111% of IOB used,
    secondly how can i reduce IOB usage?

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  2. #2
    Advanced Member level 3
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    Re: how can we reduce IOB in FPGA

    IOB = input/output buffer -- the physical pins on the part. This issue occurs because the tools will default to automatic IOB insertion. There should be synthesis options to disable automatic IO insertion for the purposes of making an IP core.



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