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Calibre LVS VDD! for digital block and VDDD for analog block

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snfvsd

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Hi All,

I am trying to do top level CALIBRE LVS for a mixed signal chip. The digital block netlist (created by PNR tool) returns a netlist in which the standard cells use VDD! and VSS! notation, for e.g. a cellnetlist from the standard cell library does does not have power pins defined in the cell pins. In the analog block I just use VDDD and GNDD.
Currently I get incorrect port errors and CALIBRE finds VSS!, VDD! in the source but not in layout (in the top digital layout I have connected digital power to VDDD and GNDD). My feeling is that I have to somehow edit the netlist to map GNDD to VSS! and VDDD to VDD!. I have already tried to add this to the cdl netlist:

.GLOBAL VDD! VSS!
.CONNECT VSS! GNDD
.GLOBAL VDD! VDDD

Any ideas will be helpful!
 

Hi,

"GLOBAL" is used in the netlist because your standard cells has pins to both "VDD!" & "VSS!".

The tool is just regarding "VDD!" & "VDDD" as separate nets (similarly with your grounds).
I believe the issue is due to the tool thinking you're shorting unrelated nets.

Is it intentionally in your design to connect the analog & digital power directly (same for the ground)?

I-FAB
 

snfvsd said:
Hi All,

I am trying to do top level CALIBRE LVS for a mixed signal chip. The digital block netlist (created by PNR tool) returns a netlist in which the standard cells use VDD! and VSS! notation, for e.g. a cellnetlist from the standard cell library does does not have power pins defined in the cell pins. In the analog block I just use VDDD and GNDD.
Currently I get incorrect port errors and CALIBRE finds VSS!, VDD! in the source but not in layout (in the top digital layout I have connected digital power to VDDD and GNDD). My feeling is that I have to somehow edit the netlist to map GNDD to VSS! and VDDD to VDD!. I have already tried to add this to the cdl netlist:

.GLOBAL VDD! VSS!
.CONNECT VSS! GNDD
.GLOBAL VDD! VDDD

Any ideas will be helpful!
Click to expand...

You Should have one global VDD/VDDO and VSS/VSSO> and for these you should have double guard ring(Deep N-well) for isolation purpose.
 

snfvsd said:
Hi All,

I am trying to do top level CALIBRE LVS for a mixed signal chip. The digital block netlist (created by PNR tool) returns a netlist in which the standard cells use VDD! and VSS! notation, for e.g. a cellnetlist from the standard cell library does does not have power pins defined in the cell pins. In the analog block I just use VDDD and GNDD.
Currently I get incorrect port errors and CALIBRE finds VSS!, VDD! in the source but not in layout (in the top digital layout I have connected digital power to VDDD and GNDD). My feeling is that I have to somehow edit the netlist to map GNDD to VSS! and VDDD to VDD!. I have already tried to add this to the cdl netlist:

.GLOBAL VDD! VSS!
.CONNECT VSS! GNDD
.GLOBAL VDD! VDDD

Any ideas will be helpful!
Click to expand...


simple way is rename the Source name such that they are of pattern VSS: or VDD: (Like VSS:0 and VSS:3) and then add following lines to your LVS rule file
VIRTUAL CONNECT COLON YES
VIRTUAL CONNECT NAME "VDD" "VSS"
Or if you want to use the same name use LVS power name and ground name statement inside Rule file. Search for it in SVRF. Modifying anything in netlist won't work.
 

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