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how to load a design into primetime and perform timing analysis

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vimalraj205

vimalraj205

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hai friends


i am a newbie to use primetime for timing analysis ......
i have my verilog , library files and sdc file how to load these into primetime

i went in this order

read_verilog
read_lib
read_sdc


but when i give report_timing


it says there is no constraints

can anybody please help me to work on it



thank you in advance
 

If the tool complain that there is no constraints, so check you constraint file and make sure you constraint your design. That's all.

Thanks.
 

hei b4 that is it possible to do STA on verilog files? You should synthesis it and input the netlist to primetime which can be in *.v format. But not RTL files directly. Correct me if wrong.
 

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