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    FIFO with simultaneous R/W - best implementation

    Hello All,

    Recently I was asked on the interview the following question: "How many memory is required to build a Synchronous FIFO of 32 bits in width and 256K in depth? The FIFO should support simultaneous Read/Write operation"

    What's the correct answer? I think that two memories of 32x256K are required in order to support simultaneous operation. Correct?

    Thank you!

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    Re: FIFO with simultaneous R/W - best implementation

    Lets consider our FIFO implemented as a circular buffer. In general, with a FIFO of length N it is possible to read and write simultaneously if it is not full or empty. In the case of empty you can write but there is nothing to read, and in the case of full you will be potentially writing over the value you are trying to read. One way around this is to increase the FIFO length to N + 1. This way there will always be at least one position between the head and tail of the circular buffer allowing for the ability to write to the tail while simultaneously reading from the head without conflict.

    In order to implement a 32-bit x 256K FIFO with simultaneous read and write requires (256K + 1) 32-bit words to implement.



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    Re: FIFO with simultaneous R/W - best implementation

    Thank you sdonecker for your comment. But emphasis was in simultaneous read/write operation. as far as I know, it's not impossible on the regular memories. the read/write operations should be enabled on the same clock from both sides.
    So, how many memories are required for the implementation of the 32x256K FIFO?
    Thank you



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    Re: FIFO with simultaneous R/W - best implementation




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    Re: FIFO with simultaneous R/W - best implementation

    The provided above link is not for SIMULTANEOUS read/write operation. In order to support simultaneous operation, the FIFO memory should be duplicated. Am I wrong?



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    Re: FIFO with simultaneous R/W - best implementation

    Hi,

    I see three possible options:

    1.) use a dual port memory (means a memory which has two access port, this is normally available in ASIC technologies) I think this is out of scope of the interview question
    2.) access a singel port memory with double speed (so you can do two memory access during one fifo access) For this you would need a double clock or work on falling edge
    3.) us a single memory which is 64x128k and add a latch logic at the input and output (this works because a fifo has no random access pattern, but a sequential access pattern) Take care if your application writes odd numbers of data into the fifo.

    For curiosity:
    How does the design look like if you use two memory. I see no advantages, because depending on the offest between read and write you may still need to read from the same memory

    regards



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    Re: FIFO with simultaneous R/W - best implementation

    can u help me with this ques...
    Data is coming at a rate of 600mhz and is transmitted at 150mhz.Calculate the size of the FIFO required to avoid the overflow if 200 data bits are coming at a time and no data is received until the previous data is completely transmitted?



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    Re: FIFO with simultaneous R/W - best implementation

    you would need a buffer of 150 entries depth.
    Method-I:
    200/600M - time required to receive 200 bits with 600MHz clock
    (200/600M)*150M=50 - number of bits, which could be transmitted during a receive phase
    200-50=150 - required buffer size
    Method-II:
    150M/600M=1/4 - effective bit rate
    200*1/4=50
    200-50=150
    Last edited by ivlsi; 20th October 2012 at 13:22.



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    Re: FIFO with simultaneous R/W - best implementation

    @qieda

    Hello,

    I am curious about this question. I didn't really understood your 2nd answer. Do you mean that we are writing on positive edge and reading on negative edge of the clock.? Is it possible.?

    Abhishek



    Quote Originally Posted by qieda View Post
    Hi,

    I see three possible options:

    1.) use a dual port memory (means a memory which has two access port, this is normally available in ASIC technologies) I think this is out of scope of the interview question
    2.) access a singel port memory with double speed (so you can do two memory access during one fifo access) For this you would need a double clock or work on falling edge
    3.) us a single memory which is 64x128k and add a latch logic at the input and output (this works because a fifo has no random access pattern, but a sequential access pattern) Take care if your application writes odd numbers of data into the fifo.

    For curiosity:
    How does the design look like if you use two memory. I see no advantages, because depending on the offest between read and write you may still need to read from the same memory

    regards



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    Re: FIFO with simultaneous R/W - best implementation

    Hi adhiverma812

    to be honest I never did such a design.

    When writing this I thought to do something like this.

    This requires that the SRAM has a combinatorical read path (it is more like a register array).
    With this you could do read and writes


    Normally SRAM will need a clock.
    For that you would need to implement a clock doubling for the SRAM (clock doubling is often discussed in the forum)
    Than you could do something like this.


    best regards



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