[SOLVED] What is change parameter and define verilog syntax to synthesis.

Hi all

What exactly exchange for define, parameter verilog syntax on synthesis?

Also, what is constant propagation?

Define, replace a name versus a number to have more readable code.
Parameter is like the generic in VHDL, to have a module parametrisable.
The constant propagation is used during synthesis, to reduce logic by propagated the constant through boundary.

u24c02 said:

Hi all

What exactly exchange for define, parameter verilog syntax on synthesis?

Also, what is constant propagation?

Click to expand...

For your query regarding 'define and parameter, go through this thread : https://www.edaboard.com/threads/72802/

Constant Propagation :
Constant propagation is a very effective technique for area minimization,since it forces the synthesis tools to optimize the logic in both forward and backward directions.Since the area minimization is achieved using constants, this technique is called constant propagation. An example of constant propagation is shown below:

Constant propagation is a very effective technique for area minimization,since it forces the synthesis tools to optimize the logic in both forward and backward directions. Since the area minimization is achieved using constants, this technique is called constant propagation. An example of constant propagation is shown below:

module const_prop (in1, in2, out1, out2);

input in1, in2;
output out1, out2;

parameter create_logic = 0;

assign out1 = (create_logic == 1) ? in1 & in2 : 1'b0;
assign out2 = (create_logic == 1) ? in1 | in2 : 1'b0;

endmodule

Note that create_logic is a parameter within the module, that controls the logic backwards from both the outputs out1 and out2. It could also control the logic forward from the inputs in1 and in2 by adding internal wires to either select the direct input in1 or the 1’b0. An example of how the forward constant propagation works is as follows:

wire int_in1, int_in2;

assign int_in1 = (create_logic == 1) ? in1 : 1'b0;
assign int_in2 = (create_logic == 1) ? in2 : 1'b0;

assign out1 = int_in1 & int_in2;
assign out2 = int_in1 | int_in2;

When this parameter is 0, it forces the logic zero in the assign statements, it results in logic zero propagation in either direction. As a result, no logic gets enabled and the logic is optimized in synthesis. When this parameter is 1, the logic is synthesized. Note that different techniques to override the parameter will also work,that is, the constant propagation will be effective, even with parameter override. Hence, the default value of the parameter can be set to 1, and be overridden to 0, by different parameter overriding techniques, when required to minimize the area.

Reference : Verilog FAQ (Shivkumar Chonnad, Needamangalam Balachander)
https://www.amazon.com/Verilog-Frequently-Questions-Applications-Extensions/dp/0387228349