FPGA Challenges ????

Dear All,

I think most of you are experienced FPGA designers. So Could you please write about most challenging issues in your FPGA designs.

Documentation and refactoring.

mrflibble said:

Documentation and refactoring.

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Very Cool. But I meant technical challenges!!!

Because we all know refactoring is a sociological and political challenge, right?

Zerox100 said:

Very Cool. But I meant technical challenges!!!

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These are the biggest technical challenge.
We have old designs with no documentation, so changing them, without documentation, or without the origional engineers still working here, it is very hard to make changes.

Zerox100 said:

Very Cool. But I meant technical challenges!!!

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From my experience, the biggest technical challenge resides in laying out the board. Careful considerations must be made concerning clock placment, signal routing, etc. I used a board once that had multiple signals running under the clock. Furthermore, the clock was placed very closely to multiple voltage regulators. At higher frequencies, the clock would be become extremely noisy. This specific FPGA dev. board, although claiming to support designs up to 130 MHz, became wholly unreliable at around 85 MHz due to the poor layout.

I found an excellent article that discussed some of the considerations when designing a PCB with an FPGA on it...
**broken link removed**

Regards,
Willis

But oh alright, if you want something a bit more "technical" ... getting the constraints right for a design and maintenance of constraints. The latter is annoying (at least in xilinx country) because the tools are suboptimal IMO. Especially when using verilog. At least with VHDL you can use attributes, which can be generated where needed for large consecutive blocks of logic. In verilog no such luck, since there's no verilog equivalent for it.


The value for the vhdl attribute can be generated by a function/generate/whatever should you so choose. In verilog the (* *) style (or comment style for that matter) attributes do not allow this unfortunately. So you have to resort to putting chunks of it in the UCF. The lazyest workable method I could come up with is to have a chunk of ucf code that I auto-generate with a perl script. Less pretty but at least it does it's job. I haven't gotten around to playing with this in system verilog. Hopefully you can generate constraints in SV as well...

Moderate side-track: Has anyone around here played with Vivado yet? If so, what's the SV support like?